Vertical digit line for semiconductor devices

ABSTRACT

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The vertically oriented digit lines are formed in direct electrical contact with the first source/drain regions of the horizontally oriented access devices. A vertically oriented body contact line is integrated to form the body contact to the body region of the horizontally oriented access device and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, and moreparticularly, to a vertical digit line for semiconductor devices.

BACKGROUND

Memory is often implemented in electronic systems, such as computers,cell phones, hand-held devices, etc. There are many different types ofmemory, including volatile and non-volatile memory. Volatile memory mayrequire power to maintain its data and may include random-access memory(RAM), dynamic random-access memory (DRAM), static random-access memory(SRAM), and synchronous dynamic random-access memory (SDRAM).Non-volatile memory may provide persistent data by retaining stored datawhen not powered and may include NAND flash memory, NOR flash memory,nitride read only memory (NROM), phase-change memory (e.g., phase-changerandom access memory), resistive memory (e.g., resistive random-accessmemory), cross-point memory, ferroelectric random-access memory (FeRAM),or the like.

As design rules shrink, less semiconductor space is available tofabricate memory, including DRAM arrays. A respective memory cell forDRAM may include an access device, e.g., transistor, having a first anda second source/drain regions separated by a channel region. A gate mayoppose the channel region and be separated therefrom by a gatedielectric. An access line, such as a word line, is electricallyconnected to the gate of the DRAM cell. A DRAM cell can include astorage node, such as a capacitor cell, coupled by the access device toa digit line. The access device can be activated (e.g., to select thecell) by an access line coupled to the access transistor. The capacitorcan store a charge corresponding to a data value of a respective cell(e.g., a logic “1” or “0”).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of a vertical three dimensional (3D)memory in accordance a number of embodiments of the present disclosure.

FIG. 2 is a perspective view illustrating a portion of a digit line andbody contact for semiconductor devices in accordance with a number ofembodiments of the present disclosure.

FIGS. 3A-3B illustrate a portion of a digit line and body contact forsemiconductor devices in accordance with a number of embodiments of thepresent disclosure.

FIG. 4 is a cross-sectional view for forming arrays of verticallystacked memory cells, at multiple stages of a semiconductor fabricationprocess, to form vertical digit lines for semiconductor devices inaccordance with a number of embodiments of the present disclosure.

FIGS. 5A-5B illustrate an example method, at one stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 6A to 6E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 7A to 7E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 8A to 8E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 9A to 9E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 10A to 10E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 11A to 11E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 12A to 12E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 13A to 13B illustrate cross sectional views of an examplehorizontally oriented access device coupled to a horizontally orientedaccess lines, having vertical digit lines for semiconductor devices, inaccordance with a number of embodiments of the present disclosure.

FIGS. 14A to 14B illustrate cross sectional views of an examplehorizontally oriented access device coupled to a horizontally orientedaccess lines, having vertical digit lines for semiconductor devices, inaccordance with a number of embodiments of the present disclosure.

FIG. 15 illustrates a cross sectional view of an example horizontallyoriented access device coupled to a horizontally oriented access lines,having vertical digit lines for semiconductor devices, in accordancewith a number of embodiments of the present disclosure.

FIGS. 16A to 16B illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having vertical digit lines for semiconductordevices and horizontally oriented access lines, in accordance with anumber of embodiments of the present disclosure.

FIGS. 17A to 17B illustrate top views of an example horizontallyoriented access device coupled to a horizontally oriented access lines,having vertical digit lines for semiconductor devices, in accordancewith a number of embodiments of the present disclosure.

FIG. 18 is a block diagram of an apparatus in the form of a computingsystem including a memory device in accordance with a number ofembodiments of the present disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure describe a digit line and bodycontact for semiconductor devices. A vertically oriented digit line isformed with horizontally oriented access devices and access lines in anarray of vertically stacked memory cells. The horizontal access devicesare integrated with horizontally oriented access lines and integratedwith vertically oriented digit lines. The body contact may be formed toprovide better body bias control to a body region of the horizontallyoriented access device, e.g., transistor. This further provides betteraccess device channel control to a silicon-oxide channel access deviceand device refresh improvement.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the figure number of the drawing and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, reference numeral104 may reference element “04” in FIG. 1, and a similar element may bereferenced as 204 in FIG. 2. Multiple analogous elements within onefigure may be referenced with a reference numeral followed by a hyphenand another numeral or a letter. For example, 302-1 may referenceelement 302-1 in FIGS. 3 and 302-2 may reference element 302-2, whichmay be analogous to element 302-1. Such analogous elements may begenerally referenced without the hyphen and extra numeral or letter. Forexample, elements 302-1 and 302-2 or other analogous elements may begenerally referenced as 302.

FIG. 1 is a block diagram of an apparatus in accordance a number ofembodiments of the present disclosure. FIG. 1 illustrates a circuitdiagram showing a cell array of a three dimensional (3D) semiconductormemory device according to embodiments of the present disclosure. FIG. 1illustrates a cell array may have a plurality of sub cell arrays 101-1,101-2, . . . , 101-N. The sub cell arrays 101-1, 101-2, . . . , 101-Nmay be arranged along a second direction (D2) 105. Each of the sub cellarrays, e.g., sub cell array 101-2, may include a plurality of accesslines 107-1, 107-2, . . . , 107-Q (which also may be referred to awordlines). Also, each of the sub cell arrays, e.g., sub cell array101-2, may include a plurality of digit lines 103-1, 103-2, . . . ,103-Q (which also may be referred to as bitlines, data lines, or senselines). In FIG. 1, the access lines 107-1, 107-2, . . . , 107-Q areillustrated extending in a first direction (D1) 109 and the digit lines103-1, 103-2, . . . , 103-Q are illustrated extending in a thirddirection (D3) 111. According to embodiments, the first direction (D1)109 and the second direction (D2) 105 may be considered in a horizontal(“X-Y”) plane. The third direction (D3) 111 may be considered in avertical (“Z”) plane. Hence, according to embodiments described herein,the digit lines 103-1, 103-2, . . . , 103-Q are extending in a verticaldirection, e.g., third direction (D3) 111.

A memory cell, e.g., 110, may include an access device, e.g., accesstransistor, and a storage node located at an intersection of each accessline 107-1, 107-2, . . . , 107-Q and each digit line 103-1, 103-2, . . ., 103-Q. Memory cells may be written to, or read from, using the accesslines 107-1, 107-2, . . . , 107-Q and digit lines 103-1, 103-2, . . . ,103-Q. The access lines 107-1, 107-2, . . . , 107-Q may conductivelyinterconnect memory cells along horizontal rows of each sub cell array101-, 101-2, . . . , 101-N, and the digit lines 103-1, 103-2, . . . ,103-Q may conductively interconnect memory cells along vertical columnsof each sub cell array 101-, 101-2, . . . , 101-N. One memory cell, e.g.110, may be located between one access line, e.g., 107-2, and one digitline, e.g., 103-2. Each memory cell may be uniquely addressed through acombination of an access line 107-1, 107-2, . . . , 107-Q and a digitline 103-1, 103-2, . . . , 103-Q.

The access lines 107-1, 107-2, . . . , 107-P may be or includeconducting patterns (e.g., metal lines) disposed on and spaced apartfrom a substrate. The access lines 107-1, 107-2, . . . , 107-Q mayextend in a first direction (D1) 109. The access lines 107-1, 107-2, . .. , 107-Q in one sub cell array, e.g., 101-2, may be spaced apart fromeach other in a vertical direction, e.g., in a third direction (D3) 111.

The digit lines 103-1, 103-2, . . . , 103-Q may be or include conductivepatterns (e.g., metal lines) extending in a vertical direction withrespect to the substrate, e.g., in a third direction (D3) 111. The digitlines in one sub cell array, e.g., 101-2, may be spaced apart from eachother in the first direction (D1) 109.

A gate of a memory cell, e.g., memory cell 110, may be connected to anaccess line, e.g., 107-2, and a first conductive node, e.g., firstsource/drain region, of an access device, e.g., transistor, of thememory cell 110 may be connected to a digit line, e.g., 103-2. Each ofthe memory cells, e.g., memory cell 110, may be connected to a storagenode, e.g., capacitor. A second conductive node, e.g., secondsource/drain region, of the access device, e.g., transistor, of thememory cell 110 may be connected to the storage node, e.g., capacitor.While first and second source/drain region reference are used herein todenote two separate and distinct source/drain regions, it is notintended that the source/drain region referred to as the “first” and/or“second” source/drain regions have some unique meaning. It is intendedonly that one of the source/drain regions is connected to a digit line,e.g., 103-2, and the other may be connected to a storage node.

FIG. 2 illustrates a perspective view showing a three dimensional (3D)semiconductor memory device, e.g., a portion of a sub cell array 101-2shown in FIG. 1 as a vertically oriented stack of memory cells in anarray, according to some embodiments of the present disclosure. FIG. 2illustrates a perspective view showing unit cell, e.g., memory cell 110shown in FIG. 1, of the 3D semiconductor memory device shown in FIG. 2.

As shown in FIG. 2, a substrate 200 may have formed thereon one of theplurality of sub cell arrays, e.g., 101-2, described in connection withFIG. 1. For example, the substrate 200 may be or include a siliconsubstrate, a germanium substrate, or a silicon-germanium substrate, etc.Embodiments, however, are not limited to these examples.

As shown in the example embodiment of FIG. 2, the substrate 200 may havefabricated thereon a vertically oriented stack of memory cells, e.g.,memory cell 110 in FIG. 1, extending in a vertical direction, e.g.,third direction (D3) 111. According to some embodiments the verticallyoriented stack of memory cells may be fabricated such that each memorycell, e.g., memory cell 110 in FIG. 1, is formed on plurality ofvertical levels, e.g., a first level (L1), a second level (L2), and athird level (L3). The repeating, vertical levels, L1, L2, and L3, may bearranged, e.g., “stacked”, a vertical direction, e.g., third direction(D3) 111 shown in FIG. 1, and may be separated from the substrate 200 byan insulator material 220. Each of the repeating, vertical levels, L1,L2, and L3 may include a plurality of discrete components, e.g.,regions, to the horizontally oriented access devices 230, e.g.,transistors, and storage nodes, e.g., capacitors, including access line107-1, 107-2, . . . , 107-Q connections and digit line 103-1, 103-2, . .. , 103-Q connections. The plurality of discrete components to thehorizontally oriented access devices 230, e.g., transistors, may beformed in a plurality of iterations of vertically, repeating layerswithin each level, as described in more detail below in connection withFIGS. 4A-4K, and may extend horizontally in the second direction (D2)205, analogous to second direction (D2) 105 shown in FIG. 1.

The plurality of discrete components to the laterally oriented accessdevices 230, e.g., transistors, may include a first source/drain region221 and a second source/drain region 223 separated by a channel region225, extending laterally in the second direction (D2) 205, and formed ina body of the access devices. In some embodiments, the channel region225 may include silicon, germanium, silicon-germanium, and/or indiumgallium zinc oxide (IGZO). In some embodiments, the first and the secondsource/drain regions, 221 and 223, can include an n-type dopant regionformed in a p-type doped body to the access device to form an n-typeconductivity transistor. In some embodiments, the first and the secondsource/drain regions, 221 and 223, may include a p-type dopant formedwithin an n-type doped body to the access device to form a p-typeconductivity transistor. By way of example, and not by way oflimitation, the n-type dopant may include Phosphorous (P) atoms and thep-type dopant may include atoms of Boron (B) formed in an oppositelydoped body region of polysilicon semiconductor material. Embodiments,however, are not limited to these examples.

The storage node 227, e.g., capacitor, may be connected to onerespective end of the access device. As shown in FIG. 2, the storagenode 227, e.g., capacitor may be connected to the second source/drainregion 223 of the access device. The storage node may be or includememory elements capable of storing data. Each of the storage nodes maybe a memory element using one of a capacitor, a magnetic tunnel junctionpattern, and/or a variable resistance body which includes a phase changematerial, etc. Embodiments, however, are not limited to these examples.In some embodiments, the storage node associated with each access deviceof a unit cell, e.g., memory cell 110 in FIG. 1, may similarly extend inthe second direction (D2) 205, analogous to second direction (D2) 105shown in FIG. 1.

As shown in FIG. 2 a plurality of horizontally oriented access lines207-1, 207-2, . . . , 207-Q extend in the first direction (D1) 209,analogous to the first direction (D1) 109 in FIG. 1. The plurality ofhorizontally oriented access lines 207-1, 207-2, . . . , 207-Q may beanalogous to the access lines 107-1, 107-2, . . . , 107-Q shown inFIG. 1. The plurality of horizontally oriented access lines 207-1,207-2, . . . , 207-Q may be arranged, e.g., “stacked”, along the thirddirection (D3) 211. The plurality of horizontally oriented access lines207-1, 207-2, . . . , 207-Q may include a conductive material. Forexample, the conductive material may include one or more of a dopedsemiconductor, e.g., doped silicon, doped germanium, etc., a conductivemetal nitride, e.g., titanium nitride, tantalum nitride, etc., a metal,e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt(Co), molybdenum (Mo), etc., and/or a metal-semiconductor compound,e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.Embodiments, however, are not limited to these examples.

Among each of the vertical levels, (L1) 213-1, (L2) 213-2, and (L3)213-P, the horizontally oriented memory cells, e.g., memory cell 110 inFIG. 1, may be spaced apart from one another horizontally in the firstdirection (D1) 209. However, as described in more detail below inconnection with FIG. 4 et. seq., the plurality of discrete components tothe horizontally oriented access devices 230, e.g., first source/drainregion 221 and second source/drain region 223 separated by a channelregion 225, extending laterally in the second direction (D2) 205, andthe plurality of horizontally oriented access lines 207-1, 207-2, . . ., 207-Q extending laterally in the first direction (D1) 209, may beformed within different vertical layers within each level. For example,the plurality of horizontally oriented access lines 207-1, 207-2, . . ., 207-Q, extending in the first direction (D1) 209, may be formed on atop surface opposing and electrically coupled to the channel regions225, separated therefrom by a gate dielectric, and orthogonal tohorizontally oriented access devices 230, e.g., transistors, extendingin laterally in the second direction (D2) 205. In some embodiments, theplurality of horizontally oriented access lines 207-1, 207-2, . . . ,207-Q, extending in the first direction (D1) 209 are formed in a highervertical layer, farther from the substrate 200, within a level, e.g.,within level (L1), than a layer in which the discrete components, e.g.,first source/drain region 221 and second source/drain region 223separated by a channel region 225, of the horizontally oriented accessdevice are formed.

As shown in the example embodiment of FIG. 2, the digit lines, 203-1,203-2, . . . , 203-Q, extend in a vertical direction with respect to thesubstrate 200, e.g., in a third direction (D3) 211. Further, as shown inFIG. 2, the digit lines, 203-1, 203-2, . . . , 203-Q, in one sub cellarray, e.g., sub cell array 101-2 in FIG. 1, may be spaced apart fromeach other in the first direction (D1) 209. The digit lines, 203-1,203-2, . . . , 203-Q, may be provided, extending vertically relative tothe substrate 200 in the third direction (D3) 211 in vertical alignmentwith source/drain regions to serve as first source/drain regions 221 or,as shown, be vertically adjacent first source/drain regions 221 for eachof the horizontally oriented access devices 230, e.g., transistors,extending laterally in the second direction (D2) 205, but adjacent toeach other on a level, e.g., first level (L1), in the first direction(D1) 209. Each of the digit lines, 203-1, 203-2, . . . , 203-Q, mayvertically extend, in the third direction (D3), on sidewalls, adjacentfirst source/drain regions 221, of respective ones of the plurality ofhorizonatally oriented access devices 230, e.g., transistors, that arevertically stacked. In some embodiments, the plurality of verticallyoriented digit lines 203-1, 203-2, . . . , 203-Q, extending in the thirddirection (D3) 211, may be connected to side surfaces of the firstsource/drain regions 221 directly and/or through additional contactsincluding metal silicides.

For example, and as shown in more detail in FIG. 2, a first one of thevertically extending digit lines, e.g., 203-1, may be adjacent asidewall of a first source/drain region 221 to a first one of thehorizontally oriented access devices 230, e.g., transistors, in thefirst level (L1) 213-1, a sidewall of a first source/drain region 221 ofa first one of the horizontally oriented access devices 230, e.g.,transistors, in the second level (L2) 213-2, and a sidewall of a firstsource/drain region 221 a first one of the horizontally oriented accessdevices 230, e.g., transistors, in the third level (L3) 213-P, etc.Similarly, a second one of the vertically extending digit lines, e.g.,203-2, may be adjacent a sidewall to a first source/drain region 221 ofa second one of the horizontally oriented access devices 230, e.g.,transistors, in the first level (L1) 213-1, spaced apart from the firstone of horizontally oriented access devices 230, e.g., transistors, inthe first level (L1) 213-1 in the first direction (D1) 209. And thesecond one of the vertically extending digit lines, e.g., 203-2, may beadjacent a sidewall of a first source/drain region 221 of a second oneof the laterally oriented access devices 230, e.g., transistors, in thesecond level (L2) 213-2, and a sidewall of a first source/drain region221 of a second one of the horizontally oriented access devices 230,e.g., transistors, in the third level (L3) 213-P, etc. Embodiments arenot limited to a particular number of levels.

The vertically extending digit lines, 203-1, 203-2, . . . , 203-Q, mayinclude a conductive material, such as, for example, one of a dopedsemiconductor material, a conductive metal nitride, metal, and/or ametal-semiconductor compound. The digit lines, 203-1, 203-2, . . . ,203-Q, may correspond to digit lines (DL) described in connection withFIG. 1.

As shown in the example embodiment of FIG. 2, a conductive body contactmay be formed extending in the first direction (D1) 209 along an endsurface of the horizontally oriented access devices 230, e.g.,transistors, in each level (L1) 213-1, (L2) 213-2, and (L3) 213-P abovethe substrate 200. The body contact may be connected to a body (as shownby 336 in FIG. 3) e.g., body region, of the horizontally oriented accessdevices 230, e.g., transistors, in each memory cell, e.g., memory cell110 in FIG. 1. The body contact may include a conductive material suchas, for example, one of a doped semiconductor material, a conductivemetal nitride, metal, and/or a metal-semiconductor compound.

Although not shown in FIG. 2, an insulating material may fill otherspaces in the vertically stacked array of memory cells. For example, theinsulating material may include one or more of a silicon oxide material,a silicon nitride material, and/or a silicon oxynitride material, etc.Embodiments, however, are not limited to these examples.

FIG. 3A illustrates in more detail a unit cell, e.g., memory cell 110 inFIG. 1, of the vertically stacked array of memory cells, e.g., within asub cell array 101-2 in FIG. 1, according to some embodiments of thepresent disclosure. As shown in FIG. 3A, the first and the secondsource/drain regions, 321 and 323, may be impurity doped regions to thelaterally oriented access devices 330, e.g., transistors. The first andthe second source/drain regions, 321 and 323, may be analogous to thefirst and the second source/drain regions 221 and 223 shown in FIG. 2.The first and the second source/drain regions may be separated by achannel 325 formed in a body of semiconductor material, e.g., bodyregion, of the horizontally oriented access devices 330, e.g.,transistors. The first and the second source/drain regions, 321 and 323,may be formed from an n-type or p-type dopant doped in the body region.Embodiments are not so limited.

For example, for an n-type conductivity transistor construction the bodyregion of the laterally oriented access devices 330, e.g., transistors,may be formed of a low doped p-type (p−) semiconductor material. In oneembodiment, the body region and the channel 325 separating the first andthe second source/drain regions, 321 and 323, may include a low doped,p-type (e.g., low dopant concentration (p−)) polysilicon materialconsisting of boron (B) atoms as an impurity dopant to thepolycrystalline silicon. The first and the second source/drain regions,321 and 323, may also comprise a metal, and/or metal composite materialscontaining ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti),copper (Cu), a highly doped degenerate semiconductor material, and/or atleast one of indium oxide (In₂O₃), or indium tin oxide(In_(2-x)Sn_(x)O₃), formed using an atomic layer deposition process,etc. Embodiments, however, are not limited to these examples. As usedherein, a degenerate semiconductor material is intended to mean asemiconductor material, such as polysilicon, containing a high level ofdoping with significant interaction between dopants, e.g., phosphorus(P), boron (B), etc. Non-degenerate semiconductors, by contrast, containmoderate levels of doping, where the dopant atoms are well separatedfrom each other in the semiconductor host lattice with negligibleinteraction.

In this example, the first and the second source/drain regions, 321 and321, may include a high dopant concentration, n-type conductivityimpurity (e.g., high dopant (n+)) doped in the first and the secondsource/drain regions, 321 and 323. In some embodiments, the high dopant,n-type conductivity first and second drain regions 321 and 323 mayinclude a high concentration of phosphorus (P) atoms deposited therein.Embodiments, however, are not limited to this example. In otherembodiments, the horizontally oriented access devices 330, e.g.,transistors, may be of a p-type conductivity construction in which casethe impurity, e.g., dopant, conductivity types would be reversed.

As shown in the example embodiment of FIG. 3A, the first source/drainregion 321 may occupy an upper portion in the body of the laterallyoriented access devices 330, e.g., transistors. For example, the firstsource/drain region 321 may have a bottom surface within the body of thehorizontally oriented access device 330 which is located higher,vertically in the third direction (D3) 311, than a bottom surface of thebody of the laterally, horizontally oriented access device 330. As such,the laterally, horizontally oriented transistor 330 may have a bodyportion which is below the first source/drain region 321 and is inelectrical contact with the body contact. Further, as shown in theexample embodiment of FIG. 3A, an access line, e.g., 307-1, analogous tothe access lines 207-1, 207-2, . . . , 207-Q in FIGS. 2 and 107-1,107-2, . . . , 107-Q shown in FIG. 1, may disposed on a top surfaceopposing and coupled to a channel region 325, separated therefrom by agate dielectric 304. The gate dielectric material 304 may include, forexample, a high-k dielectric material, a silicon oxide material, asilicon nitride material, a silicon oxynitride material, etc., or acombination thereof. Embodiments are not so limited. For example, inhigh-k dielectric material examples the gate dielectric material 304 mayinclude one or more of hafnium oxide, hafnium silicon oxide, lanthanumoxide, zirconium oxide, zirconium silicon oxide, tantalum oxide,titanium oxide, barium strontium titanium oxide, barium titanium oxide,strontium titanium oxide, lithium oxide, aluminum oxide, lead scandiumtantalum oxide, lead zinc niobite, etc.

As shown in the example embodiment of FIG. 3A, a digit line, e.g.,303-1, analogous to the digit lines 203-1, 203-2, . . . , 203-Q in FIGS.2 and 103-1, 103-2, . . . , 103-Q in FIG. 1, may be vertically extendingin the third direction (D3) 311 adjacent a sidewall of the firstsource/drain region 321 in the body to the horizontally oriented accessdevices 330, e.g., transistors horizontally conducting between the firstand the second source/drain regions 321 and 323 along the seconddirection (D2) 305. In this embodiment, the vertically oriented digitline 303-1 is formed asymmetrically adjacent in electrical contact withthe first source/drain regions 321. The digit line 303-1 may be formedas asymmetrically to reserve room for a body contact in the channelregion 325.

FIG. 3B illustrates in more detail a unit cell, e.g., memory cell 110 inFIG. 1, of the vertically stacked array of memory cells, e.g., within asub cell array 101-2 in FIG. 1, according to some embodiments of thepresent disclosure. As shown in FIG. 3B, the first and the secondsource/drain regions, 321 and 323, may be impurity doped regions to thelaterally oriented access devices 330, e.g., transistors. The first andthe second source/drain regions, 321 and 323, may be analogous to thefirst and the second source/drain regions 221 and 223 shown in FIG. 2and the first and the second source/drain regions 321 and 323 shown inFIG. 3A. The first and the second source/drain regions may be separatedby a channel 325 formed in a body of semiconductor material, e.g., bodyregion, of the horizontally oriented access devices 330, e.g.,transistors. The first and the second source/drain regions, 321 and 323,may be formed from an n-type or p-type dopant doped in the body region.Embodiments are not so limited.

As shown in the example embodiment of FIG. 3B, a digit line, e.g.,303-1, analogous to the digit lines 203-1, 203-2, . . . , 203-Q in FIGS.2 and 103-1, 103-2, . . . , 103-Q in FIG. 1, may be vertically extendingin the third direction (D3) 311 adjacent a sidewall of the firstsource/drain region 321 in the body to the horizontally oriented accessdevices 330, e.g., transistors horizontally conducting between the firstand the second source/drain regions 321 and 323 along the seconddirection (D2) 305. In this embodiment, the vertically oriented digitline 303-1 is formed symmetrically, in vertical alignment, in electricalcontact with the first source/drain region 321. The digit line 303-1 maybe formed in contact with an insulator material such that there is nobody contact within channel 325.

As shown in the example embodiment of FIG. 3B, the digit line 303-1 maybe formed symmetrically within the first source/drain region 321 suchthat the first source/drain region 321 surrounds the digit line 303-1all around. The first source/drain region 321 may occupy an upperportion in the body of the laterally oriented access devices 330, e.g.,transistors. For example, the first source/drain region 321 may have abottom surface within the body of the horizontally oriented accessdevice 330 which is located higher, vertically in the third direction(D3) 311, than a bottom surface of the body of the laterally,horizontally oriented access device 330. As such, the laterally,horizontally oriented transistor 330 may have a body portion which isbelow the first source/drain region 321 and is in contact with the bodycontact. An insulator material may fill the body contact such that thefirst source/drain region 321 may not be in electrical contact withchannel 325. Further, as shown in the example embodiment of FIG. 3B, anaccess line, e.g., 307-1, analogous to the access lines 207-1, 207-2, .. . , 207-Q in FIGS. 2 and 107-1, 107-2, . . . , 107-Q shown in FIG. 1,may disposed on a top surface opposing and coupled to a channel region325, separated therefrom by a gate dielectric 304.

FIG. 4 is a cross-sectional view, at one stage of a semiconductorfabrication process, for forming vertical digit lines for semiconductordevices having horizontally oriented access devices and horizontallyoriented access lines, such as illustrated in FIGS. 1-3, and inaccordance with a number of embodiments of the present disclosure.

In the example embodiment shown in the example of FIG. 4, the methodcomprises depositing alternating layers of a first dielectric material,430-1, 430-2, . . . , 430-N (collectively referred to as firstdielectric material 430), a semiconductor material, 432-1, 432-2, . . ., 432-N (collectively referred to as semiconductor material 432), and asecond dielectric material, 433-1, 433-2, . . . , 433-N (collectivelyreferred to as second dielectric 433), in repeating iterations to form avertical stack 401 on a working surface of a semiconductor substrate400. The alternating materials in the repeating, vertical stack 401 maybe separated from the substrate 400 by an insulator material 420. In oneembodiment, the first dielectric material 430 can be deposited to have athickness, e.g., vertical height in the third direction (D3), in a rangeof twenty (20) nanometers (nm) to sixty (60) nm. In one embodiment, thesemiconductor material 432 can be deposited to have a thickness, e.g.,vertical height, in a range of twenty (20) nm to one hundred (100) nm.In one embodiment, the second dielectric material 433 can be depositedto have a thickness, e.g., vertical height, in a range of ten (10) nm tothirty (30) nm. Embodiments, however, are not limited to these examples.As shown in FIG. 4, a vertical direction 411 is illustrated as a thirddirection (D3), e.g., z-direction in an x-y-z coordinate system,analogous to the third direction (D3), among first, second, and thirddirections, shown in FIGS. 1-3.

In some embodiments, the first dielectric material, 430-1, 430-2, . . ., 430-N, may be an interlayer dielectric (ILD). By way of example, andnot by way of limitation, the first dielectric material, 430-1, 430-2, .. . , 430-N, may comprise an oxide material, e.g., SiO₂. In anotherexample the first dielectric material, 430-1, 430-2, . . . , 430-N, maycomprise a silicon nitride (Si₃N₄) material (also referred to herein as“SiN”). In another example the first dielectric material, 430-1, 430-2,. . . , 430-N, may comprise a silicon oxy-carbide (SiO_(x)C_(y))material. In another example the first dielectric material, 430-1,430-2, . . . , 430-N, may include silicon oxy-nitride (SiO_(x)N_(y))material (also referred to herein as “SiON”), and/or combinationsthereof. Embodiments are not limited to these examples.

In some embodiments, the semiconductor material, 432-1, 432-2, . . . ,432-N, may comprise a silicon (Si) material in a polycrystalline and/oramorphous state. The semiconductor material, 432-1, 432-2, . . . ,432-N, may be a low doped, p-type (p−) silicon material. Thesemiconductor material, 432-1, 432-2, . . . , 432-N, may be formed bygas phase doping boron atoms (B), as an impurity dopant, at a lowconcentration to form the low doped, p-type (p−) silicon material. Thelow doped, p-type (p−) silicon material may be a polysilicon material.Embodiments, however, are not limited to these examples.

In some embodiments, the second dielectric material, 433-1, 433-2, . . ., 433-N, may be an interlayer dielectric (ILD). By way of example, andnot by way of limitation, the second dielectric material, 433-1, 433-2,. . . , 433-N, may comprise a nitride material. The nitride material maybe a silicon nitride (Si₃N₄) material (also referred to herein as“SiN”). In another example the second dielectric material, 433-1, 433-2,. . . , 433-N, may comprise a silicon oxy-carbide (SiOC) material. Inanother example the second dielectric material, 433-1, 433-2, . . . ,433-N, may include silicon oxy-nitride (SiON), and/or combinationsthereof. Embodiments are not limited to these examples. However,according to embodiments, the second dielectric material, 433-1, 433-2,. . . , 433-N, is purposefully chosen to be different in material orcomposition than the first dielectric material, 430-1, 430-2, . . . ,430-N, such that a selective etch process may be performed on one of thefirst and second dielectric layers, for example the other one of thefirst and the second dielectric layers and/or semiconductor material432, e.g., the second SiN dielectric material, 433-1, 433-2, . . . ,433-N, may be selectively etched relative to the semiconductor material,432-1, 432-2, . . . , 432-N, and a first oxide dielectric material,430-1, 430-2, . . . , 430-N.

The repeating iterations of alternating first dielectric material,430-1, 430-2, . . . , 430-N layers, semiconductor material, 432-1,432-2, . . . , 432-N layers, and second dielectric material, 433-1,433-2, . . . , 433-N layers may be deposited according to asemiconductor fabrication process such as chemical vapor deposition(CVD) in a semiconductor fabrication apparatus. Embodiments, however,are not limited to this example and other suitable semiconductorfabrication techniques may be used to deposit the alternating layers ofa first dielectric material, a semiconductor material, and a seconddielectric material, in repeating iterations to form the vertical stack401.

The layers may occur in repeating iterations vertically. In the exampleof FIG. 4, three tiers, numbered 1, 2, and 3, of the repeatingiterations are shown. For example, the stack may include: a firstdielectric material 430-1, a semiconductor material 432-1, a seconddielectric material 433-1, a third dielectric material 430-2, a secondsemiconductor material 432-2, a fourth dielectric material 433-2, afifth dielectric material 430-3, a third semiconductor material 432-3,and a sixth dielectric material 433-3. As such, a stack may include: afirst oxide material 430-1, a first semiconductor material 432-1, afirst nitride material 433-1, a second oxide material 430-2, a secondsemiconductor material 432-2, a second nitride material 433-2, a thirdoxide material 430-3, a third semiconductor material 432-3, and a thirdnitride material 433-3 in further repeating iterations. Embodiments,however, are not limited to this example and more or fewer repeatingiterations may be included.

FIG. 5A illustrates an example method, at one stage of a semiconductorfabrication process, for forming arrays of vertically stacked memorycells, having horizontally oriented access devices and horizontallyoriented access lines with vertically oriented digit lines, such asillustrated in FIGS. 1-3, and in accordance with a number of embodimentsof the present disclosure. FIG. 5A illustrates a top down view of asemiconductor structure, at a particular point in time, in asemiconductor fabrication process, according to one or more embodiments.In the example embodiment shown in the example of FIG. 5A, the methodcomprises using an etchant process to form a plurality of first verticalopenings 500, having a first horizontal direction (D1) 509 and a secondhorizontal direction (D2) 505, through the vertical stack to thesubstrate. In one example, as shown in FIG. 5A, the plurality of firstvertical openings 500 are extending predominantly in the secondhorizontal direction (D2) 505 and may form elongated vertical, pillarcolumns 513-1, 513-2, . . . , 513-M (collectively and/or independentlyreferred to as 513), with sidewalls 514 in the vertical stack. Theplurality of first vertical openings 500 may be formed usingphotolithographic techniques to pattern a photolithographic mask 537,e.g., to form a hard mask (HM), on the vertical stack prior to etchingthe plurality of first vertical openings 500. Similar semiconductorprocess techniques may be used at other points of the semiconductorfabrication process described herein.

The openings 500 may be filled with a dielectric material 539. In oneexample, a spin on dielectric process may be used to fill the openings500. In one embodiment, the dielectric material 539 may be an oxidematerial. However, embodiments are not so limited.

FIG. 5B is a cross sectional view, taken along cut-line A-A′ in FIG. 5A,showing another view of the semiconductor structure at a particular timein the semiconductor fabrication process. The cross sectional view shownin FIG. 5B shows the repeating iterations of alternating layers of afirst dielectric material, 530-1, 530-2, . . . , 530-N, a semiconductormaterial, 532-1, 532-2, . . . , 532-N, and a second dielectric material,533-1, 533-2, . . . , 533-N, on a semiconductor substrate 500 to formthe vertical stack, e.g. 401 as shown in FIG. 4.

As shown in FIG. 5B, a plurality of first vertical openings may beformed through the layers within the vertically stacked memory cells toexpose vertical sidewalls in the vertical stack and form elongatedvertical pillar columns 513 and then filled with a third dielectricmaterial 539. The first vertical openings may be formed through therepeating iterations of the oxide material 530, the semiconductormaterial 532, and the nitride material 533. As such, the first verticalopenings may be formed through the first oxide material 530-1, the firstsemiconductor material 532-1, the first nitride material 533-1, thesecond oxide material 530-2, the second semiconductor material 532-2,the second nitride material 533-2, the third oxide material 530-3, thethird semiconductor material 532-3, and the third nitride material533-3. Embodiments, however, are not limited to the vertical opening(s)shown in FIG. 5B. Multiple vertical openings may be formed through thelayers of materials. The first vertical openings may be formed to exposevertical sidewalls in the vertical stack. The first vertical openingsmay extend in a second horizontal direction (D2) 505 to form elongatedvertical, pillar columns 513 with first vertical sidewalls in thevertical stack and then filled with third dielectric 539.

As shown in FIG. 5B, a third dielectric material 539, such as an oxideor other suitable spin on dielectric (SOD), may be deposited in thefirst vertical openings, using a process such as CVD, to fill the firstvertical openings. Third dielectric material 539 may also be formed froma silicon nitride (Si₃N₄) material. In another example, the thirddielectric material 539 may include silicon oxy-nitride (SiO_(x)N_(y)),and/or combinations thereof. Embodiments are not limited to theseexamples. The plurality of first vertical openings may be formed usingphotolithographic techniques to pattern a photolithographic mask 537,e.g., to form a hard mask (HM), on the vertical stack prior to etchingthe plurality of first vertical openings. In one embodiment, hard mask537 may be deposited over third dielectric material 539. In someembodiments, a subsequent photolithographic material 537, e.g., hardmask, may be deposited using CVD and planarized using CMP to cover andclose the first vertical openings over the vertical stack and theprevious hard mask 537. Similar semiconductor process techniques may beused at other points of the semiconductor fabrication process describedherein.

FIG. 6A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines with vertically oriented digit lines,such as illustrated in FIGS. 1-3, and in accordance with a number ofembodiments of the present disclosure. FIG. 6A illustrates a top downview of a semiconductor structure, at a particular point in time, in asemiconductor fabrication process, according to one or more embodiments.In the example embodiment shown in the example of FIG. 6A, the methodcomprises using an etchant process to form a plurality of first verticalopenings 600, having a first horizontal direction (D1) 609 and a secondhorizontal direction (D2) 605, through the vertical stack to thesubstrate. In one example, as shown in FIG. 6A, the plurality of firstvertical openings 600 are extending predominantly in the secondhorizontal direction (D2) 605 and may form elongated vertical, pillarcolumns 613 with sidewalls 614 in the vertical stack. The plurality offirst vertical openings 600 may be formed using photolithographictechniques to pattern a photolithographic mask 637, e.g., to form a hardmask (HM), on the vertical stack prior to etching the plurality of firstvertical openings 600.

FIG. 6B is a cross sectional view, taken along cut-line A-A′ in FIG. 6A,showing another view of the semiconductor structure at a particular timein the semiconductor fabrication process. The cross sectional view shownin FIG. 6B shows the repeating iterations of alternating layers of afirst dielectric material, 630-1, 630-2, . . . , 630-N, a semiconductormaterial, 632-1, 632-2, . . . , 632-N, and a second dielectric material,633-1, 633-2, . . . , 633-N, on a semiconductor substrate 600 to formthe vertical stack, e.g. 401 as shown in FIG. 4.

As shown in FIG. 6B, a plurality of first vertical openings may beformed through the layers within the vertically stacked memory cells toexpose vertical sidewalls in the vertical stack. The first verticalopenings may be formed through the repeating iterations of the oxidematerial 630, the semiconductor material 632, and the nitride material633. As such, the first vertical openings may be formed through thefirst oxide material 630-1, the first semiconductor material 632-1, thefirst nitride material 633-1, the second oxide material 630-2, thesecond semiconductor material 632-2, the second nitride material 633-2,the third oxide material 630-3, the third semiconductor material 632-3,and the third nitride material 633-3. Embodiments, however, are notlimited to the vertical opening(s) shown in FIG. 6B. Multiple verticalopenings may be formed through the layers of materials. The firstvertical openings may be formed to expose vertical sidewalls in thevertical stack. The first vertical openings may extend in a secondhorizontal direction (D2) 605 to form elongated vertical, pillar columnswith first vertical sidewalls in the vertical stack.

As shown in FIG. 6B, a third dielectric material 639, such as an oxideor other suitable spin on dielectric (SOD), may be deposited in thefirst vertical openings, using a process such as CVD, to fill the firstvertical openings. A photolithographic material 637, e.g., hard mask,may be deposited using CVD and planarized using chemical mechanicalplanarization (CMP) to cover and close the first vertical openings overthe vertical stack. Similar semiconductor process techniques may be usedat other points of the semiconductor fabrication process describedherein.

FIG. 6C is a cross-sectional view, at another stage of a semiconductorfabrication process, for forming vertical digit lines for semiconductordevices having horizontally oriented access devices and horizontallyoriented access lines, such as illustrated in FIGS. 1-3, and inaccordance with a number of embodiments of the present disclosure. FIG.6C illustrates a cross sectional view, taken along cut-line B-B′ in FIG.6A.

An etchant may be flowed into the second vertical opening 670 toselectively etch a portion of the second dielectric material 633. Forexample, an etchant may be flowed into the second vertical opening 670to selectively etch the nitride material 633. The etchant may target alliterations of the second dielectric material 633 within the stack. Assuch, the etchant may target the first nitride material 633-1, thesecond nitride material 633-2, and the third nitride material 633-3within the stack.

The selective etchant process may consist of one or more etchchemistries selected from an aqueous etch chemistry, a semi-aqueous etchchemistry, a vapor etch chemistry, or a plasma etch chemistries, amongother possible selective etch chemistries. For example, a dry etchchemistry of oxygen (O₂) or O₂ and sulfur dioxide (SO₂) may be utilized.As another example, a dry etch chemistries of O₂ or of O₂ and nitrogen(N₂) may be used to selectively etch the second dielectric material 633.Alternatively, or in addition, a selective etch to remove the seconddielectric material 633 may comprise a selective etch chemistry ofphosphoric acid (H₃PO₄) and/or dissolving the second dielectric material633 using a selective solvent.

The selective etchant process may etch the nitride material 633 to forma first horizontal opening 673. The selective etchant process may beperformed such that the first horizontal opening 673 has a length ordepth (DIST 1) a first distance 676 from the second vertical opening670. The first distance (DIST 1) 676 may be a further distance than usedto form a first source/drain region or a first channel region. Thesecond dielectric material 633 may be etched a first distance (DIST 1)676 in a range of approximately fifty (50) to two hundred and fifty(250) nanometers (nm) back from the second vertical opening. The firstdistance (DIST 1) 676 may be controlled by controlling time, compositionof etchant gas, and etch rate of a reactant gas flowed into the secondvertical opening 670, e.g., rate, concentration, temperature, pressure,and time parameters. As such, the nitride material 633 may be etched afirst distance 676 from the vertical opening. The selective etch may beisotropic, but selective to the second dielectric material 633,substantially stopping on the first dielectric material 630 and thesemiconductor material. Thus, in one example embodiment, the selectiveetchant process may remove substantially all of the nitride material 633from a top surface of the semiconductor material 632 to a bottom surfaceof the first dielectric material, e.g., oxide material, in a layer abovewhile etching horizontally a first distance (DIST 1) 676 from the secondvertical opening 670 adjacent a first region of the semiconductormaterial 632. In this example, the horizontal opening 673 will have aheight (H1) substantially equivalent to and be controlled by athickness, to which the second dielectric layer 633, e.g., nitridematerial, was deposited. Embodiments, however, are not limited to thisexample. As described herein, the selective etchant process may etch thenitride material 633 to a first distance (DIST 1) 676 and to a height(H1).

FIG. 6D illustrates a cross sectional view, taken along cut-line C-C′ inFIG. 6A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 6D is illustrated extending in the second horizontal direction (D2)605, outside of a region for the horizontally oriented access devicesand horizontally oriented storage nodes.

In FIG. 6E, the third dielectric material 639, such as an oxide or othersuitable spin on dielectric (SOD), may be deposited in the firstvertical openings, using a process such as CVD. The third dielectricmaterial 639 is shown spaced along a first direction (D1), extendinginto and out from the plane of the drawings sheet, for a threedimensional array of vertically oriented memory cells. A hard mask 637,which may be deposited using CVD and planarized using chemicalmechanical planarization (CMP), may be seen over the third dielectricmaterial 639. Similar semiconductor process techniques may be used atother points of the semiconductor fabrication process described herein.

FIG. 6E illustrates a cross sectional view, taken along cut-line D-D′ inFIG. 6A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 6E is illustrated, right to left in the plane of the drawing sheet,extending in the first direction (D1) 609 along an axis of the repeatingiterations of alternating layers of a first dielectric material, 630-1,630-2, . . . , 630-N and a semiconductor material, 632-1, 632-2, . . . ,632-N, intersecting across the plurality of third dielectric fillmaterial 639.

In this cross sectional view, the etched second dielectric material633-1, 633-2, . . . , 633-N may be seen such that the second dielectricmaterial 633-1, 633-2, . . . , 633-N may seem completely removed byselective etching to form first horizontal opening 673. In FIG. 6E, thethird dielectric fill material 639 is shown separating the space betweenthe first horizontal openings 673, which can be spaced along a firstdirection (D1) 609 and stacked vertically in arrays extending in thethird direction (D3) 611 in the three dimensional (3D) memory. A hardmask 637, may be deposited using CVD and planarized using chemicalmechanical planarization (CMP) to cover and close the first verticalopenings over the vertical stack.

FIG. 7A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines with vertically oriented digit lines,such as illustrated in FIGS. 1-3, and in accordance with a number ofembodiments of the present disclosure. FIG. 7A illustrates a top downview of a semiconductor structure, at a particular point in time, in asemiconductor fabrication process, according to one or more embodiments.In the example embodiment shown in FIG. 7A, the method comprises usingan etchant process to etch through the third dielectric material 739that filled in the plurality of first vertical openings 700, having afirst horizontal direction (D1) 709 and a second horizontal direction(D2) 705, through the vertical stack to the substrate. The plurality offirst vertical openings 700 may be viewed within the hard mask 737covering the working surface of the vertical semiconductor stack. Thethird dielectric material 739 may be etched to a height within the hardmask 737.

FIG. 7B is a cross sectional view, taken along cut-line A-A′ in FIG. 7A,showing another view of the semiconductor structure at a particular timein the semiconductor fabrication process. The cross sectional view shownin FIG. 7B shows the repeating iterations of alternating layers of afirst dielectric material, 730-1, 730-2, . . . , 730-N, a semiconductormaterial, 732-1, 732-2, . . . , 732-N, and a second dielectric material,733-1, 733-2, . . . , 733-N, on a semiconductor substrate 700.

As shown in FIG. 7B, a plurality of first vertical openings may beformed through the layers within the vertically stacked memory cells toexpose vertical sidewalls in the vertical stack. The first verticalopenings may be formed through the repeating iterations of the oxidematerial 730, the semiconductor material 732, and the nitride material733. As such, the first vertical openings may be formed through thefirst oxide material 730-1, the first semiconductor material 732-1, thefirst nitride material 733-1, the second oxide material 730-2, thesecond semiconductor material 732-2, the second nitride material 733-2,the third oxide material 730-3, the third semiconductor material 732-3,and the third nitride material 733-3. Embodiments, however, are notlimited to the vertical opening(s) shown in FIG. 7B. Multiple verticalopenings may be formed through the layers of materials. The firstvertical openings may be formed to expose vertical sidewalls in thevertical stack. The first vertical openings may extend in a secondhorizontal direction (D2) 705 to form elongated vertical, pillar columnswith first vertical sidewalls in the vertical stack.

As shown in FIG. 7B, a third dielectric material 739, such as an oxideor other suitable spin on dielectric (SOD), may be viewed in the firstvertical openings, filling the first vertical openings. A hard mask 737may be deposited to cover and close the first vertical openings over thevertical stack. Similar semiconductor process techniques may be used atother points of the semiconductor fabrication process described herein.

FIG. 7C is a cross-sectional view, at another stage of a semiconductorfabrication process, for forming vertical digit lines for semiconductordevices having horizontally oriented access devices and horizontallyoriented access lines, such as illustrated in FIGS. 1-3, and inaccordance with a number of embodiments of the present disclosure. FIG.7C illustrates a cross sectional view, taken along cut-line B-B′ in FIG.7A.

The second dielectric material 733 may be selectively etched in thesecond horizontal direction (D2) 705 to form a plurality of firsthorizontal openings 773. An etchant may be flowed into the secondvertical opening 770 to selectively etch a portion of the seconddielectric material 733. As such, the etchant may target the firstnitride material 733-1, the second nitride material 733-2, and the thirdnitride material 733-3 within the stack. The selective etchant processmay etch the nitride material 733 to form a first horizontal opening773. The selective etchant process may etch the nitride material 733 toa first distance (DIST 1) 776 and to a height (H1).

A gate dielectric material 738 may be deposited in the plurality offirst horizontal openings 773 created by the etched second dielectricmaterial 733. The gate dielectric material 738 may be conformallydeposited on the semiconductor material 732 with a lateral exhume. Agate dielectric material 738 may be conformally deposited in theplurality of first horizontal openings 773 using a chemical vapordeposition (CVD) process, plasma enhanced CVD (PECVD), atomic layerdeposition (ALD), or other suitable deposition process, to cover abottom surface and the vertical sidewalls of the plurality of firsthorizontal openings 773. In another embodiment, gate dielectric material738 may be thermally grown onto a surface of semiconductor material 732.By way of example, and not by way of limitation, the gate dielectric 738may comprise a silicon dioxide (SiO2) material, aluminum oxide (Al₂O₃)material, high dielectric constant (k), e.g., high-k, dielectricmaterial, and/or combinations thereof.

FIG. 7D illustrates a cross sectional view, taken along cut-line C-C′ inFIG. 7A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 7D is illustrated extending in the second horizontal direction (D2)705, outside of a region for the horizontally oriented access devicesand horizontally oriented storage nodes.

In FIG. 7D, the third dielectric material 739 is shown filling the spacealong a first direction (D1), extending into and out from the plane ofthe drawings sheet, for a three dimensional array of vertically orientedmemory cells. A portion of the third dielectric material 739 may beetched in a horizontal direction to view repeating iterations ofalternating layers of a first dielectric material, 730-1, 730-2, . . . ,730-N and a semiconductor material, 732-1, 732-2, . . . , 732-N. Alateral punch may be applied to the dielectric material 739 to etchthrough. The cross sectional view shown in FIG. 7D is illustrated, rightto left in the plane of the drawing sheet, extending in the firstdirection (D1) 709 along an axis of the repeating iterations ofalternating layers of a first dielectric material, 730-1, 730-2, . . . ,730-N and a semiconductor material, 732-1, 732-2, . . . , 732-N,intersecting the third dielectric fill material 739. The hard mask 737over the repeating iterations of alternating layers of a firstdielectric material, 730-1, 730-2, . . . , 730-N and a semiconductormaterial, 732-1, 732-2, . . . , 732-N may be viewed over thirddielectric material 739.

FIG. 7E illustrates a cross sectional view, taken along cut-line D-D′ inFIG. 7A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 7E is illustrated, right to left in the plane of the drawing sheet,extending in the first direction (D1) 709 along an axis of the repeatingiterations of alternating layers of a first dielectric material, 730-1,730-2, . . . , 730-N and a semiconductor material, 732-1, 732-2, . . . ,732-N, intersecting across the plurality of third dielectric fillmaterial 739.

In FIG. 7E, the third dielectric fill material 739 is shown separatingthe space between the first horizontal openings 773, and can be spacedalong a first direction (D1) 709 and stacked vertically in arraysextending in the third direction (D3) 711 in the three dimensional (3D)memory. A portion of the third dielectric material 739 may be etchedvertically. A portion of the third dielectric fill 739 within theplurality of first vertical openings may be removed. The openingscreated by the etched third dielectric material 739 may form continuoussecond horizontal openings 779 that extend in the first horizontaldirection 709. A hard mask 737, covering the first vertical openingsover the vertical stack may be etched in the same manner as the thirddielectric material 739.

FIG. 8A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines with vertically oriented digit lines,such as illustrated in FIGS. 1-3, and in accordance with a number ofembodiments of the present disclosure. FIG. 8A illustrates a top downview of a semiconductor structure, at a particular point in time, in asemiconductor fabrication process, according to one or more embodiments.In the example embodiment shown in FIG. 8A, the method comprises usingan etchant process to etch through the third dielectric material 839that filled in the plurality of first vertical openings 800, having afirst horizontal direction (D1) 809 and a second horizontal direction(D2) 805, through the vertical stack to the substrate. The plurality offirst vertical openings 800 may be viewed within the hard mask 837covering the working surface of the vertical semiconductor stack. Thethird dielectric material 839 may be etched to a height between cut-lineA-A′ and cut-line D-D′ within the hard mask 837. A first conductivematerial 877 may be deposited above the plurality of first verticalopenings 800.

FIG. 8B is a cross sectional view, taken along cut-line A-A′ in FIG. 8A,showing another view of the semiconductor structure at a particular timein the semiconductor fabrication process. The cross sectional view shownin FIG. 8B shows the repeating iterations of alternating layers of afirst dielectric material, 830-1, 830-2, . . . , 830-N, a semiconductormaterial, 832-1, 832-2, . . . , 832-N, and a second dielectric material,833-1, 833-2, . . . , 833-N, on a semiconductor substrate 800.

As shown in FIG. 8B, a plurality of first vertical openings may beformed through the layers within the vertically stacked memory cells toexpose vertical sidewalls in the vertical stack. The first verticalopenings may be formed through the repeating iterations of the oxidematerial 830, the semiconductor material 832, and the nitride material833. As such, the first vertical openings may be formed through thefirst oxide material 830-1, the first semiconductor material 832-1, thefirst nitride material 833-1, the second oxide material 830-2, thesecond semiconductor material 832-2, the second nitride material 833-2,the third oxide material 830-3, the third semiconductor material 832-3,and the third nitride material 833-3. Embodiments, however, are notlimited to the vertical opening(s) shown in FIG. 8B. Multiple verticalopenings may be formed through the layers of materials. The firstvertical openings may be formed to expose vertical sidewalls in thevertical stack. The first vertical openings may extend in a secondhorizontal direction (D2) 805 to form elongated vertical, pillar columnswith first vertical sidewalls in the vertical stack.

As shown in FIG. 8B, a third dielectric material 839, such as an oxideor other suitable spin on dielectric (SOD), may be viewed in the firstvertical openings, filling the first vertical openings. A firstconductive material 877 may be deposited over hard mask 837 covering thefirst vertical openings. Similar semiconductor process techniques may beused at other points of the semiconductor fabrication process describedherein.

FIG. 8C is a cross-sectional view, at another stage of a semiconductorfabrication process, for forming vertical digit lines for semiconductordevices having horizontally oriented access devices and horizontallyoriented access lines, such as illustrated in FIGS. 1-3, and inaccordance with a number of embodiments of the present disclosure. FIG.8C illustrates a cross sectional view, taken along cut-line B-B′ in FIG.8A.

A first conductive material, 877-1, 877-2, . . . , 877-N (collectivelyreferred to as first conductive material 877), may be deposited on thegate dielectric material 838 and may be so entwined as to beindistinguishable. The first conductive material 877 may be conformallydeposited into a portion of the second vertical opening 870, using achemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD),atomic layer deposition (ALD), or other suitable deposition process,such that the first conductive material 877 may also be deposited intothe first horizontal opening.

In some embodiments, the first conductive material, 877-1, 877-2, . . ., 877-N, may comprise one or more of a doped semiconductor, e.g., dopedsilicon, doped germanium, etc., a conductive metal nitride, e.g.,titanium nitride, tantalum nitride, etc., a metal, e.g., tungsten (W),titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum(Mo), etc., and/or a metal-semiconductor compound, e.g., tungstensilicide, cobalt silicide, titanium silicide, etc, and/or some othercombination thereof as also described in FIG. 3. The first conductivematerial 877 entwined with the gate dielectric material 838 may formhorizontally oriented access lines opposing a channel region of thesemiconductor material, such as shown as access lines 103-1, 103-2, . .. , 103-Q (which also may be referred to a wordlines).

FIG. 8D illustrates a cross sectional view, taken along cut-line C-C′ inFIG. 8A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 8D is illustrated extending in the second horizontal direction (D2)805, outside of a region for the horizontally oriented access devicesand horizontally oriented storage nodes.

In FIG. 8D, the third dielectric material 839 is shown filling the spacealong a first direction (D1), extending into and out from the plane ofthe drawings sheet, for a three dimensional array of vertically orientedmemory cells. The cross sectional view shown in FIG. 8D is illustrated,right to left in the plane of the drawing sheet, extending in the firstdirection (D1) 809 along an axis of the repeating iterations ofalternating layers of a first conductive material, 877-1, 877-2, . . . ,877-N, a first dielectric material, 830-1, 830-2, . . . , 830-N, and asemiconductor material, 832-1, 832-2, . . . , 832-N, intersecting thethird dielectric fill material 839. The first conductive material,877-1, 877-2, . . . , 877-N, may fill the openings created by the etchedsecond dielectric material 833. That is, the first conductive material,877-1, 877-2, . . . , 877-N, may be seen in the second vertical opening870. The first conductive material, 877-1, 877-2, . . . , 877-N, may beconformally deposited using a chemical vapor deposition (CVD) process,plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or othersuitable deposition process, such that the first conductive material 877may also be deposited into the first horizontal opening 873. The firstconductive material 877 may be entwined with a gate dielectric material838.

The hard mask 837 over the repeating iterations of alternating layers ofa first dielectric material, 877-1, 877-2, . . . , 877-N, and asemiconductor material, 832-1, 832-2, . . . , 832-N, may be viewed overthird dielectric material 839. The first conductive material, 877-1,877-2, . . . , 877-N, may be deposited over the hard mask 837.

FIG. 8E illustrates a cross sectional view, taken along cut-line D-D′ inFIG. 8A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 8E is illustrated, right to left in the plane of the drawing sheet,extending in the first direction (D1) 809 along an axis of the repeatingiterations of alternating layers of a first conductive material, 877-1,877-2, . . . , 877-N entwined with a gate dielectric material 838, afirst dielectric material, 830-1, 830-2, . . . , 830-N, and asemiconductor material, 832-1, 832-2, . . . , 832-N, intersecting acrossthe plurality of third dielectric fill material 839.

In FIG. 8E, the first conductive material, 877-1, 877-2, . . . , 877-N,is shown filling in the space in the second vertical opening 870 left bythe etched portion of the second dielectric (illustrated as 533 in FIG.5). Third dielectric fill material 839 is shown spaced along a firstdirection (D1) 809 and stacked vertically in arrays extending in thethird direction (D3) 811 in the three dimensional (3D) memory. The firstconductive material, 877-1, 877-2, . . . , 877-N, entwined with a gatedielectric material 838, may fill the openings created by the etchedsecond dielectric material 833. A hard mask 837, covering the firstvertical openings over the vertical stack may be etched in the samemanner as the third dielectric material 839. The first conductivematerial, 877-1, 877-2, . . . , 877-N, may be deposited over the hardmask 837.

FIG. 9A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines with vertically oriented digit lines,such as illustrated in FIGS. 1-3, and in accordance with a number ofembodiments of the present disclosure. FIG. 8A illustrates a top downview of a semiconductor structure, at a particular point in time, in asemiconductor fabrication process, according to one or more embodiments.In the example embodiment shown in FIG. 9A, the method comprises usingan etchant process to etch through the first conductive material, 977-1,977-2, . . . , 977-N, that was formed over the third dielectric material939 in the plurality of first vertical openings 900, having a firsthorizontal direction (D1) 909 and a second horizontal direction (D2)905, through the vertical stack to the substrate. The third dielectricmaterial 939 may be etched back vertically to the cut-line D-D′. Theplurality of first vertical openings 900 may be viewed within the hardmask 937 covering the working surface of the vertical semiconductorstack.

FIG. 9B is a cross sectional view, taken along cut-line A-A′ in FIG. 9A,showing another view of the semiconductor structure at a particular timein the semiconductor fabrication process. The cross sectional view shownin FIG. 9B shows the repeating iterations of alternating layers of afirst dielectric material, 930-1, 930-2, . . . , 930-N, a semiconductormaterial, 932-1, 932-2, . . . , 932-N, and a second dielectric material,933-1, 933-2, . . . , 933-N, on a semiconductor substrate 900.

As shown in FIG. 9B, a plurality of first vertical openings may beformed through the layers within the vertically stacked memory cells toexpose vertical sidewalls in the vertical stack. The first verticalopenings may be formed through the repeating iterations of the oxidematerial 930, the semiconductor material 932, and the nitride material933. As such, the first vertical openings may be formed through thefirst oxide material 930-1, the first semiconductor material 932-1, thefirst nitride material 933-1, the second oxide material 930-2, thesecond semiconductor material 932-2, the second nitride material 933-2,the third oxide material 930-3, the third semiconductor material 932-3,and the third nitride material 933-3. Embodiments, however, are notlimited to the vertical opening(s) shown in FIG. 9B. Multiple verticalopenings may be formed through the layers of materials. The firstvertical openings may be formed to expose vertical sidewalls in thevertical stack. The first vertical openings may extend in a secondhorizontal direction (D2) 905 to form elongated vertical, pillar columnswith first vertical sidewalls in the vertical stack.

As shown in FIG. 9B, a third dielectric material 939, such as an oxideor other suitable spin on dielectric (SOD), may be viewed in the firstvertical openings, filling the first vertical openings. A firstconductive material 977 may be deposited over hard mask 937 covering thefirst vertical openings. Similar semiconductor process techniques may beused at other points of the semiconductor fabrication process describedherein.

FIG. 9C is a cross-sectional view, at another stage of a semiconductorfabrication process, for forming vertical digit lines for semiconductordevices having horizontally oriented access devices and horizontallyoriented access lines, such as illustrated in FIGS. 1-3, and inaccordance with a number of embodiments of the present disclosure. FIG.9C illustrates a cross sectional view, taken along cut-line B-B′ in FIG.9A.

The first conductive material, 977-1, 977-2, . . . , 977-N, may berecessed back in the first horizontal opening 973, e.g., etched awayfrom the second vertical opening 970 using an atomic layer etching (ALE)or other suitable technique. In some examples, the first conductivematerial 977 may be etched back in the horizontal opening 973 a seconddistance (DIST 2) 983 into the continuous second horizontal openings979. The first conductive material 977 may be etched back in thehorizontal opening 973 a second distance (DIST 2) 983 for a range oftwenty (20) to one hundred and fifty (150) nanometers (nm) back from thesecond vertical opening 970. The first conductive material 877 may beselectively etched, leaving the oxide material 930, a portion of thefirst conductive material 977, and the semiconductor material 932intact. In some embodiments, the first conductive material 977 may beetched using an atomic layer etching (ALE) process. In some embodiments,the first conductive material 977 may be etched using an isotropic etchprocess. For example, the first conductive material 977 may be recesseda second distance (DIST 2) 983 back into the continuous secondhorizontal openings 979 extending in the first horizontal directionusing an atomic layer etching (ALE) process

The first conductive material 977 may be recessed the second distance(DIST 2) 983 back in the first horizontal opening 973 to remain indirect contact with the remaining portion of the nitride material 933and on a top surface of the semiconductor material 932. As such, thefirst conductive material 977 entwined with the gate dielectric material938 may form horizontally oriented access lines opposing a channelregion of the semiconductor material.

FIG. 9D illustrates a cross sectional view, taken along cut-line C-C′ inFIG. 9A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 9D is illustrated extending in the second horizontal direction (D2)905, outside of a region for the horizontally oriented access devicesand horizontally oriented storage nodes.

In FIG. 9D, the third dielectric material 939 is shown filling the spacealong a first direction (D1), extending into and out from the plane ofthe drawings sheet, for a three dimensional array of vertically orientedmemory cells. The cross sectional view shown in FIG. 9D is illustrated,right to left in the plane of the drawing sheet, extending in the firstdirection (D1) 909 along an axis of the repeating iterations ofalternating layers of an etched portion of the first conductivematerial, 977-1, 977-2, . . . , 977-N, a first dielectric material,930-1, 930-2, . . . , 930-N, and a semiconductor material, 932-1, 932-2,. . . , 932-N, intersecting the third dielectric fill material 939. Thefirst conductive material, 977-1, 977-2, . . . , 977-N, may fill theopenings created by the etched second dielectric material 933. The firstconductive material, 977-1, 977-2, . . . , 977-N, may be recessed backin the first horizontal opening 973, e.g., etched away from the secondvertical opening 970. The hard mask 937 over the repeating iterations ofalternating layers of a first dielectric material, 930-1, 930-2, . . . ,930-N, and a semiconductor material, 932-1, 932-2, . . . , 932-N, may beviewed over third dielectric material 939. The first conductivematerial, 977-1, 977-2, . . . , 977-N, (deposited over the hard mask 937in FIG. 8D) may be etched away.

FIG. 9E illustrates a cross sectional view, taken along cut-line D-D′ inFIG. 9A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 9E is illustrated, right to left in the plane of the drawing sheet,extending in the first direction (D1) 809 along an axis of the repeatingiterations of alternating layers of a first conductive material, 977-1,977-2, . . . , 977-N entwined with a gate dielectric material 938, afirst dielectric material, 930-1, 930-2, . . . , 930-N, and asemiconductor material, 932-1, 932-2, . . . , 932-N, intersecting acrossthe plurality of third dielectric fill material 939.

In FIG. 9E, the first conductive material, 977-1, 977-2, . . . , 977-N,is shown filling in the space in the second vertical opening 970 left bythe etched portion of the second dielectric. Third dielectric fillmaterial 939 is shown spaced along a first direction (D1) 909 andstacked vertically in arrays extending in the third direction (D3) 911in the three dimensional (3D) memory. The first conductive material,977-1, 977-2, . . . , 977-N, may fill the openings created by the etchedsecond dielectric material 933. A hard mask 937, covering the firstvertical openings over the vertical stack may be etched in the samemanner as the third dielectric material 939. The first conductivematerial, 977-1, 977-2, . . . , 977-N, may be deposited over the hardmask 937.

FIG. 10A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines with vertically oriented digit lines,such as illustrated in FIGS. 1-3, and in accordance with a number ofembodiments of the present disclosure. FIG. 10A illustrates a top downview of a semiconductor structure, at a particular point in time, in asemiconductor fabrication process, according to one or more embodiments.In the example embodiment shown in FIG. 10A, the method comprisesdepositing a fourth dielectric material 1074 above the etched firstconductive material 1077. The method further comprises depositing a highdoped semiconductor material 1095 over the hard mask 1037, the fourthdielectric material 1074 within the plurality of first vertical openings1000, having a first horizontal direction (D1) 1009 and a secondhorizontal direction (D2) 1005, through the vertical stack to thesubstrate. The third dielectric material 1039 formed within plurality offirst vertical openings 1000 may be viewed covering the working surfaceof the vertical semiconductor stack.

FIG. 10B is a cross sectional view, taken along cut-line A-A′ in FIG.10A, showing another view of the semiconductor structure at a particulartime in the semiconductor fabrication process. The cross sectional viewshown in FIG. 10B shows the repeating iterations of alternating layersof a first dielectric material, 1030-1, 1030-2, . . . , 1030-N, asemiconductor material, 1032-1, 1032-2, . . . , 1032-N, and a seconddielectric material, 1033-1, 1033-2, . . . , 1033-N, on a semiconductorsubstrate 1000.

As shown in FIG. 10B, a plurality of first vertical openings may beformed through the layers within the vertically stacked memory cells toexpose vertical sidewalls in the vertical stack. The first verticalopenings may be formed through the repeating iterations of the oxidematerial 1030, the semiconductor material 1032, and the nitride material1033. As such, the first vertical openings may be formed through thefirst oxide material 1030-1, the first semiconductor material 1032-1,the first nitride material 1033-1, the second oxide material 1030-2, thesecond semiconductor material 1032-2, the second nitride material1033-2, the third oxide material 1030-3, the third semiconductormaterial 1032-3, and the third nitride material 1033-3. Embodiments,however, are not limited to the vertical opening(s) shown in FIG. 10B.Multiple vertical openings may be formed through the layers ofmaterials. The first vertical openings may be formed to expose verticalsidewalls in the vertical stack. The first vertical openings may extendin a second horizontal direction (D2) 1005 to form elongated vertical,pillar columns with third vertical sidewalls in the vertical stack.

As shown in FIG. 10B, a third dielectric material 1039, such as an oxideor other suitable spin on dielectric (SOD), may be viewed in the firstvertical openings, filling the first vertical openings. Similarsemiconductor process techniques may be used at other points of thesemiconductor fabrication process described herein.

FIG. 10C is a cross-sectional view, at another stage of a semiconductorfabrication process, for forming vertical digit lines for semiconductordevices having horizontally oriented access devices and horizontallyoriented access lines, such as illustrated in FIGS. 1-3, and inaccordance with a number of embodiments of the present disclosure. FIG.10C illustrates a cross sectional view, taken along cut-line B-B′ inFIG. 10A.

A fourth dielectric material 1074 may be conformally deposited, e.g.,using a CVD process, into the first horizontal opening 1073 adjacent thefirst conductive material 1077, e.g., horizontal, conductive access lineextending in the first direction (D1) 109 in FIG. 1. In someembodiments, the fourth dielectric material 1074 may be below the firstdielectric material 1030, above the low doped semiconductor material1032. The fourth dielectric material 1074 may be in direct contact withthe first conductive material 1077 and the low doped semiconductormaterial 1032. Embodiments, however, are not limited to this example.

The fourth dielectric material 1074 may be the same material or adifferent material as the second dielectric material 1033. For example,the second dielectric material 1033 may be Si₃N₄ and the fourthdielectric material 1074 may also be Si₃N₄. In another example, thefourth dielectric material 1074 may comprise a silicon dioxide (SiO₂)material. In another example, the fourth dielectric material 1074 maycomprise a silicon oxy-carbide (SiO_(x)C_(y)) material. In anotherexample, the fourth dielectric material 1074 may include siliconoxy-nitride (SiO_(x)N_(y)), and/or combinations thereof. Embodiments arenot limited to these examples.

A high doped semiconductor material 1095 may be deposited into thesecond vertical opening (as illustrated by 970 in FIG. 9) to form aconductive body contact with the low doped, e.g., p-type, low doped(p−), semiconductor material 1032. The high doped semiconductor material1095 may also be in contact with the fourth dielectric material 1074 andthe first dielectric material 1030. In some embodiments, the high dopedsemiconductor material 1095 may be a metal such as tungsten (W).Embodiments, however, are not so limited. In some embodiments, the highdoped semiconductor material 1095 may be a high doped, e.g., p-type,high doped (p+), semiconductor material that may be deposited into thesecond vertical opening. In this example, the high doped semiconductormaterial 1095 may be a high doped, p-type (p+) silicon material. Thehigh doped, p-type (p+) silicon material 1095 may be a polysiliconmaterial. In one example, forming the high doped semiconductor material1095 comprises depositing a degenerate semiconductor material. As usedherein, a degenerate semiconductor material is intended to mean asemiconductor material, such as polysilicon, containing a high level ofdoping with significant interaction between dopants, e.g., phosphorous(P), boron (B), etc. Non-degenerate semiconductors, by contrast, containmoderate levels of doping, where the dopant atoms are well separatedfrom each other in the semiconductor host lattice with negligibleinteraction.

In some examples, the high doped semiconductor material 1095 may be ahigh doped, p-type (p+) silicon-germanium (SiGe) material. The SiGematerial may be deposited into the second vertical opening at arelatively lower temperature. Embodiments, however, are not limited tothese examples.

FIG. 10D illustrates a cross sectional view, taken along cut-line C-C′in FIG. 10A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 10D is illustrated extending in the second horizontal direction(D2) 1005, outside of a region for the horizontally oriented accessdevices and horizontally oriented storage nodes.

In FIG. 10D, a fourth dielectric material 1074 is shown conformallydeposited, e.g., using a CVD process, into the first horizontal opening1073 adjacent the first conductive material 1077. The fourth dielectricmaterial 1074 may be in direct contact with the first conductivematerial 1077 and the low doped semiconductor material 1032. A highdoped semiconductor material 1095 may be deposited into the secondvertical opening to form a conductive body contact with the low doped,e.g., p-type, low doped (p−), semiconductor material 1032. The highdoped semiconductor material 1095 may also be in contact with the fourthdielectric material 1074 and the first dielectric material 1030.

The hard mask 1037 over the repeating iterations of alternating layersof a first dielectric material, 1030-1, 1030-2, . . . , 1030-N, aportion of the first conductive material, 1077-1, 1077-2, . . . ,1077-N, the deposited fourth dielectric material 1074, and thesemiconductor material, 1032-1, 1032-2, . . . , 1032-N may be viewedover third dielectric material 1039.

FIG. 10E illustrates a cross sectional view, taken along cut-line D-D′in FIG. 10A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 10E is illustrated, right to left in the plane of the drawingsheet, extending in the first direction (D1) 1009 along an axis of therepeating iterations of alternating layers of a first conductivematerial, 1077-1, 1077-2, . . . , 1077-N, a first dielectric material,1030-1, 1030-2, . . . , 1030-N, and a semiconductor material, 1032-1,1032-2, . . . , 1032-N, intersecting across the plurality of thirddielectric fill material 1039.

In FIG. 10E, the first conductive material, 1077-1, 1077-2, . . . ,1077-N entwined with a gate dielectric material 1038, is shown fillingin the space in the second vertical opening left by the etched portionof the second dielectric. Third dielectric fill material 1039 is shownspaced along a first direction (D1) 1009 and stacked vertically inarrays extending in the third direction (D3) 1011 in the threedimensional (3D) memory. The first conductive material, 1077-1, 1077-2,. . . , 1077-N, may fill the openings created by the etched seconddielectric material 1033. A hard mask 1037, covering the first verticalopenings over the vertical stack may be etched in the same manner as thethird dielectric material 1039. The conductive material, 1077-1, 1077-2,. . . , 1077-N, may be deposited over the hard mask 1037.

FIG. 11A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines, such as illustrated in FIGS. 1-3,and in accordance with a number of embodiments of the presentdisclosure. FIG. 11A illustrates a top down view of a semiconductorstructure, at a particular point in time, in a semiconductor fabricationprocess, according to one or more embodiments. In the example embodimentof FIG. 11A, the method comprises using a photolithographic process topattern the photolithographic mask 1137. The method in FIG. 11A furtherillustrates using one or more etchant processes to form a verticalopening 1151 in a storage node region 1150 (and 1144 in FIGS. 11A and11C) through the vertical stack and extending predominantly in the firsthorizontal direction (D1) 1109. The one or more etchant processes formsa vertical opening 1151 to expose third sidewalls in the repeatingiterations of alternating layers of a first dielectric material, 1130-1,1130-2, . . . , 1130-N, a semiconductor material, 1132-1, 1132-2, . . ., 1132-N, and a second dielectric material, 1133-1, 1133-2, . . . ,1133-N, in the vertical stack, shown in FIGS. 11B-11E, adjacent a secondregion of the semiconductor material. A first conductive material 1177may be formed above the vertical opening 1151. A fourth dielectricmaterial 1174 may be formed above the first conductive material 1177. Ahigh doped semiconductor material 1195 may be formed above the fourthdielectric material 1174.

In some embodiments, this process is performed before the semiconductorfabrication process described in connection with FIGS. 1-3. However, theembodiment shown in FIGS. 11B-11E illustrate a sequence in which thestorage node fabrication process is performed “after” the firstconductive material 1177, have already been performed, e.g., access lineformation first.

According to an example embodiment, shown in FIGS. 11B-11E, the methodcomprises forming a second vertical opening 1151 in the vertical stack(401 in FIG. 4) and selectively etching the second region 1144 of thesemiconductor material, 1132-1, 1132-2, . . . , 1132-N, to form a secondhorizontal opening 1179 a third horizontal distance back from thevertical opening 1151 in the vertical stack (401 in FIG. 4). Accordingto embodiments, selectively etching the second region 1144 of thesemiconductor material, 1132-1, 1132-2, . . . , 1132-N can compriseusing an atomic layer etching (ALE) process. As will be explained morein connection with FIG. 11C, a second source/drain region 1178 can beformed in the semiconductor material, 1132-1, 1132-2, . . . , 1132-N ata distal end of the second horizontal openings 1179 from the verticalopening.

FIG. 11B illustrates a cross sectional view, taken along cut-line A-A′in FIG. 11A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 11B is away from the plurality of separate, horizontal accesslines, 1177-1, 1177-2, . . . , 1177-N, 1177-(N+1), . . . , 1177-(Z−1),and shows repeating iterations of alternating layers of a dielectricmaterial, 1130-1, 1130-2, . . . , 1130-(N+1), a semiconductor material,1132-1, 1132-2, . . . , 1132-N, and a second dielectric material,1133-1, 1133-2, . . . , 1133-N separated by an opening 1151, on asemiconductor substrate 1100 to form the vertical stack. As shown inFIG. 11B, a vertical direction 1111 is illustrated as a third direction(D3), e.g., z-direction in an x-y-z coordinate system, analogous to thethird direction (D3) 1111, among first, second, and third directions,shown in FIGS. 1-3. The plane of the drawing sheet, extending right andleft, is in a first direction (D1) 1109. In the example embodiment ofFIG. 11B, the materials within the vertical stack—a dielectric material,1130-1, 1130-2, . . . , 1130-(N+1), a semiconductor material, 1132-1,1132-2, . . . , 1132-N, and a second dielectric material, 1133-1,1133-2, . . . , 1133-N are extending into and out of the plane of thedrawing sheet in second direction (D2) and along an axis of orientationof the horizontal access devices and horizontal storage nodes of thearrays of vertically stacked memory cells of the three dimensional (3D)memory.

FIG. 11C illustrates a cross sectional view, taken along cut-line B-B′in FIG. 11A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 11C is illustrated extending in the second horizontal direction(D2) 1105, left and right along the plane of the drawing sheet, along anaxis of the repeating iterations of alternating layers of a firstdielectric material, 1130-1, 1130-2, . . . , 1130-N, a semiconductormaterial, 1132-1, 1132-2, . . . , 1132-N, and a second dielectricmaterial, 1133-1, 1133-2, . . . , 1133-N, along and in which thehorizontally oriented access devices and horizontally oriented storagenodes, e.g., capacitor cells, can be formed within the layers ofsemiconductor material, 1132-1, 1132-2, . . . , 1132-N.

In the example embodiment of FIG. 11C, a vertical opening 1151 andhorizontal openings 1179 are shown formed from the mask, patterning andetching process described in connection with FIG. 11A. As shown in FIG.11C, the semiconductor material, 1132-1, 1132-2, . . . , 1132-N, in thesecond region 1144 has been selectively removed to form the horizontalopenings 1179. In one example, an atomic layer etching (ALE) process isused to selectively etch the semiconductor material, 1132-1, 1132-2, . .. , 1132-N, and remove a third distance back from the vertical opening1151. Horizontally oriented storage nodes, e.g., capacitor cells, may beformed, as shown in FIGS. 11A-11E, later or first, relative to thefabrication process shown in FIGS. 4-9, in the second horizontalopenings 1179.

Also shown in FIG. 11C, the first source/drain region may be formed bygas phase doping a dopant into a top surface portion of thesemiconductor material 1132. In some embodiments, the first source/drainregion may be adjacent a channel region. In one example, gas phasedoping may be used to achieve a highly isotropic e.g., non-directionaldoping, to form the second source/drain region 1178 to a horizontallyoriented access device in region 1142. In another example, thermalannealing with doping gas, such as phosphorous may be used with a highenergy plasma assist to break the bonding. Embodiments, however, are notso limited and other suitable semiconductor fabrication techniques maybe utilized. In some embodiments, the fourth dielectric material 1174may be deposited in the continuous second horizontal opening 1179adjacent the first conductive material 1177 entwined with gatedielectric material 1138.

According to one example embodiment, as shown in FIG. 11C a secondsource/drain region 1178 may be formed by flowing a high energy gasphase dopant, such as Phosphorous (P) for an n-type transistor, into thesecond horizontal openings 1179 to dope the dopant in the semiconductormaterial, 1132-1, 1132-2, . . . , 1132-N, at a distal end of the secondhorizontal openings 1179 from the vertical opening 1151. A fourthvertical opening may be formed adjacent a second region of thesemiconductor material, 1132-1, 1132-2, . . . , 1132-N, to expose thirdvertical sidewalls in the vertical stack. The semiconductor material,1132-1, 1132-2, . . . , 1132-N, may be selectively etched in the secondhorizontal direction (D2) 1105 to form a plurality of third horizontalopenings in the second region. A dopant may be doped in the side surfaceof the semiconductor material from the third horizontal openings to formthe second source/drain region 1178 horizontally adjacent the channelregion. Horizontally oriented capacitor cells having a bottom electrode(1261 as illustrated in FIG. 12) may be deposited into the thirdhorizontal opening to have electrical contact with the secondsource/drain region 1178.

As shown further in FIG. 11C, a first electrode, e.g., 1161, forhorizontally oriented storage nodes are to be coupled to the secondsource/drain regions 1178 of the horizontal access devices. As shownlater in FIG. 11C, such horizontally oriented storage nodes are shownformed in a second horizontal opening 1179 extending in second direction(D2), left and right in the plane of the drawing sheet, a third distancefrom the vertical opening 1151 formed in the vertical stack, e.g., 401in FIG. 4, and along an axis of orientation of the horizontal accessdevices and horizontal storage nodes of the arrays of vertically stackedmemory cells of the three dimensional (3D) memory. In FIG. 11C, aneighboring, opposing horizontal access line 1177-3 is illustrated by adashed line indicating a location set inward from the plane andorientation of the drawing sheet.

FIG. 11D illustrates a cross sectional view, taken along cut-line C-C′in FIG. 11A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 11D is illustrated extending in the second horizontal direction(D2) 1105, left and right in the plane of the drawing sheet, along anaxis of the repeating iterations of alternating layers of a firstdielectric material, 1130-1, 1130-2, . . . , 1130-N, a semiconductormaterial, 1132-1, 1132-2, . . . , 1132-N, and a second dielectricmaterial, 1133-1, 1133-2, . . . , 1133-N, outside of a region in whichthe horizontally oriented access devices and horizontally orientedstorage nodes, e.g., capacitor cells, will be formed within the layersof semiconductor material, 1132-1, 1132-2, . . . , 1132-N. At the leftend of the drawing sheet is shown the repeating iterations ofalternating layers of a first dielectric material, 1130-1, 1130-2, . . ., 1130-N, a semiconductor material, 1132-1, 1132-2, . . . , 1132-N, anda second dielectric material, 1133-1, 1133-2, . . . , 1133-N, at whichlocation a horizontally oriented first conductive material, e.g., accesslines 1177-1, 1177-2, . . . , 1177-N, shown in FIG. 1, et. seq., can beformed.

Again, while first and second source/drain region references are usedherein to denote two separate and distinct source/drain regions, it isnot intended that the source/drain region referred to as the “first”and/or “second” source/drain regions have some unique meaning. It isintended only that one of the source/drain regions is connected to adigit line, e.g., 107-2, and the other may be connected to a storagenode.

In some embodiments, a first conductive material 1177 may be illustratedadjacent second dielectric material 1133. The first conductive material1177 may be adjacent third dielectric material 1139. A high dopedsemiconductor material 1195 may be illustrated along the repeatingiterations of alternating layers of a first dielectric material, 1130-1,1130-2, . . . , 1130-N, a semiconductor material, 1132-1, 1132-2, . . ., 1132-N, and a second dielectric material, 1133-1, 1133-2, . . . ,1133-N.

FIG. 11E illustrates a cross sectional view, taken along cut-line D-D′in FIG. 11A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 11E is illustrated, right to left in the plane of the drawingsheet, extending in the first direction (D1) 1109 along an axis of therepeating iterations of alternating layers of a first dielectricmaterial, 1130-1, 1130-2, . . . , 1130-N, a semiconductor material,1132-1, 1132-2, . . . , 1132-N, and a second dielectric material,1133-1, 1133-2, 1133-N, intersecting across the plurality of separate,horizontal access lines, 1177-1, 1177-2, . . . , 1177-N, andintersecting regions of the semiconductor material, 1132-1, 1132-2, . .. , 1132-N, in which a channel region may be formed, separated from theplurality of separate, horizontal access lines, 1177-1, 1177-2, . . . ,1177-N, entwined into the gate dielectric material 1138. In FIG. 11E,the first dielectric fill material 1139 is shown separating the spacebetween neighboring horizontally oriented access devices which may beformed extending into and out from the plane of the drawing sheet asdescribed in connection with FIGS. 4-9, and can be spaced along a firstdirection (D1) 1109 and stacked vertically in arrays extending in thethird direction (D3) 1111 in the three dimensional (3D) memory.

FIG. 12A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines, such as illustrated in FIGS. 1-3,and in accordance with a number of embodiments of the presentdisclosure. FIG. 12A illustrates a top down view of a semiconductorstructure, at a particular point in time, in a semiconductor fabricationprocess, according to one or more embodiments.

In the example embodiment of FIG. 12A, the method comprises using aphotolithographic process to pattern the photolithographic mask 1237.The method in FIG. 12A further illustrates using one or more etchantprocesses to form a vertical opening 1251 in a storage node region 1250(and 1244 in FIGS. 12A and 12C) through the vertical stack and extendingpredominantly in the first horizontal direction (D1) 1209. The one ormore etchant processes forms a vertical opening 1251 to expose thirdsidewalls in the repeating iterations of alternating layers of a firstdielectric material, 1230-1, 1230-2, . . . , 1230-N, a semiconductormaterial, 1232-1, 1232-2, . . . , 1232-N, and a second dielectricmaterial, 1233-1, 1233-2, . . . , 1233-N, in the vertical stack, shownin FIGS. 12B-12E, adjacent a second region of the semiconductormaterial. A first conductive material 1277 may be formed above thevertical opening 1251. A fourth dielectric material 1274 may be formedabove the first conductive material 1277. A low doped semiconductormaterial 1232 may be formed above the fourth dielectric material 1274.

In some embodiments, this process is performed after selectivelyremoving an access device region of the semiconductor material in whichto form a first source/drain region, channel region, and secondsource/drain region of the horizontally oriented access devices, asillustrated in FIG. 10. According to an example embodiment, shown inFIGS. 12B-12E, the method comprises selectively etching the secondregion of the semiconductor material, 1232-1, 1232-2, . . . , 1232-N, todeposit a second source/drain region and capacitor cells through thesecond horizontal opening, which is a second horizontal distance backfrom a vertical opening 1251 in the vertical stack. In some embodiments,as shown in FIGS. 12B-12E, the method comprises forming capacitor cellas the storage node in the second horizontal opening. By way of example,and not by way of limitation, forming the capacitor comprises using anatomic layer deposition (ALD) process to sequentially deposit, in thesecond horizontal opening, a first electrode 1261 and a second electrode1256 separated by a cell dielectric 1263. Other suitable semiconductorfabrication techniques and/or storage nodes structures may be used.

FIG. 12B illustrates a cross sectional view, taken along cut-line A-A′in FIG. 12A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 12B is away from the plurality of separate, horizontal accesslines, 1277-1, 1277-2, . . . , 1277-N, 1277-(N+1), . . . , 1277-(Z−1),and shows repeating iterations of alternating layers of a dielectricmaterial, 1230-1, 1230-2, . . . , 1230-(N+1), separated by horizontallyoriented capacitor cells having first electrodes 1261, e.g., bottom cellcontact electrodes, cell dielectrics 1263, and second electrodes 1256,e.g., top, common node electrodes, on a semiconductor substrate 1200 toform the vertical stack. As shown in FIG. 8B, a vertical direction 1211is illustrated as a third direction (D3), e.g., z-direction in an x-y-zcoordinate system, analogous to the third direction (D3) 1211, amongfirst, second, and third directions, shown in FIGS. 1-3. The plane ofthe drawing sheet, extending right and left, is in a first direction(D1) 1209. In the example embodiment of FIG. 12B, the first electrodes1261, e.g., bottom electrodes to be coupled to source/drain regions ofhorizontal access devices, and second electrodes 1256 are illustratedseparated by a cell dielectric material 1263 extending into and out ofthe plane of the drawing sheet in second direction (D2) and along anaxis of orientation of the horizontal access devices and horizontalstorage nodes of the arrays of vertically stacked memory cells of thethree dimensional (3D) memory.

FIG. 12C illustrates a cross sectional view, taken along cut-line B-B′in FIG. 12A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 12C is illustrated extending in the second horizontal direction(D2) 1205, left and right along the plane of the drawing sheet, along anaxis of the repeating iterations of alternating layers of a firstdielectric material, 1230-1, 1230-2, . . . , 1230-N, a semiconductormaterial, 1232-1, 1232-2, . . . , 1232-N, and a second dielectricmaterial, 1233-1, 1233-2, . . . , 1233-N, along and in which thehorizontally oriented access devices and horizontally oriented storagenodes, e.g., capacitor cells, can be formed within the layers ofsemiconductor material, 1232-1, 1232-2, . . . , 1232-N. In the exampleembodiment of FIG. 12C, the horizontally oriented storage nodes, e.g.,capacitor cells, are illustrated as having been formed in thissemiconductor fabrication process and first electrodes 1261, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1256, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1263, are shown. However, embodiments are not limitedto this example. In other embodiments, the first electrodes 1261, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1256, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1263, may be formed subsequent to forming a firstsource/drain region, a channel region, and a second source/drain regionin a region of the semiconductor material, 1232-1, 1232-2, . . . ,1232-N, intended for location, e.g., placement formation, of thehorizontally oriented access devices, described next.

In the example embodiment of FIG. 12C, the horizontally oriented storagenodes having the first electrodes 1261, e.g., bottom electrodes to becoupled to source/drain regions of horizontal access devices, and secondelectrodes 1256, e.g., top electrodes to be coupled to a commonelectrode plane such as a ground plane, are shown formed in a secondhorizontal opening, extending in second direction (D2), left and rightin the plane of the drawing sheet, a third distance from the verticalopening, e.g., 1251 in FIG. 12B, formed in the vertical stack, e.g., 401in FIG. 4, and along an axis of orientation of the horizontal accessdevices and horizontal storage nodes of the arrays of vertically stackedmemory cells of the three dimensional (3D) memory. In FIG. 12C, aneighboring, opposing horizontal access line 1277 is illustrated by adashed line indicating a location set inward from the plane andorientation of the drawing sheet.

In some embodiments, the fourth dielectric material 1274 may be belowthe first dielectric material 1230 while remaining in direct contactwith the low doped semiconductor material 1232. The fourth dielectricmaterial 1274 may be in contact with a high doped, p-type (p+) siliconmaterial 1295, e.g., the body region contact of the horizontallyoriented access device.

FIG. 12D illustrates a cross sectional view, taken along cut-line C-C′in FIG. 12A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 12D is illustrated extending in the second horizontal direction(D2) 1205, left and right in the plane of the drawing sheet, along anaxis of the repeating iterations of alternating layers of a firstdielectric material, 1230-1, 1230-2, . . . , 1230-N, a semiconductormaterial, 1232-1, 1232-2, . . . , 1232-N, and a second dielectricmaterial, 1233-1, 1233-2, . . . , 1233-N, outside of a region in whichthe horizontally oriented access devices and horizontally orientedstorage nodes, e.g., capacitor cells, will be formed within the layersof semiconductor material, 1232-1, 1232-2, . . . , 1232-N. In FIG. 12C,the third dielectric material 1239 is shown filling the space betweenthe horizontally oriented access devices, which can be spaced along afirst direction (D1), extending into and out from the plane of thedrawings sheet, for a three dimensional array of vertically orientedmemory cells. However, in the cross sectional view of FIG. 12D, thesecond electrode 1256, e.g., top, common electrode to a capacitor cellstructure, is additionally shown present in the space betweenhorizontally neighboring devices. At the left end of the drawing sheetis shown the repeating iterations of alternating layers of a firstdielectric material, 1230-1, 1230-2, . . . , 1230-N, a semiconductormaterial, 1232-1, 1232-2, . . . , 1232-N, and a second dielectricmaterial, 1233-1, 1233-2, . . . , 1233-N, at which location a verticallyoriented digit line, e.g., digit lines 107-1, 107-2, . . . , 107-P shownin FIG. 1, et. seq., can be integrated to form electrical contact withthe second source/drain regions or digit line conductive contactmaterial, described in more detail below.

In some embodiments, a first conductive material 1277 may be illustratedadjacent second dielectric material 1233. The first conductive material1277 may be adjacent third dielectric material 1239. A body contactregion 1295 may also be illustrated along the repeating iterations ofalternating layers of a first dielectric material, 1230-1, 1230-2, . . ., 1230-N, a semiconductor material, 1232-1, 1232-2, . . . , 1232-N, anda second dielectric material, 1233-1, 1233-2, . . . , 1233-N.

FIG. 12E illustrates a cross sectional view, taken along cut-line D-D′in FIG. 12A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 12E is illustrated, right to left in the plane of the drawingsheet, extending in the first direction (D1) 1209 along an axis of therepeating iterations of alternating layers of a first dielectricmaterial, 1230-1, 1230-2, . . . , 1230-N, a semiconductor material,1232-1, 1232-2, . . . , 1232-N, and a second dielectric material,1233-1, 1233-2, . . . , 1233-N, intersecting across the plurality ofseparate, horizontal access lines, 1277-1, 1277-2, . . . , 1277-N, andintersecting regions of the semiconductor material, 1232-1, 1232-2, . .. , 1232-N, in which a channel region may be formed, separated from theplurality of separate, horizontal access lines, 1277-1, 1277-2, . . . ,1277-N, by the gate dielectric material 1238. In FIG. 12E, the firstdielectric fill material 1239 is shown separating the space betweenneighboring horizontally oriented access devices and horizontallyoriented storage nodes, which may be formed extending into and out fromthe plane of the drawing sheet as described in more detail below, andcan be spaced along a first direction (D1) 1209 and stacked verticallyin arrays extending in the third direction (D3) 1211 in the threedimensional (3D) memory.

FIG. 13A illustrates a cross sectional view, taken along cut-line B-B′in FIG. 12A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 13A is illustrated extending in the second horizontal direction(D2) 1305, left and right along the plane of the drawing sheet, along anaxis of the repeating iterations of alternating layers of a firstdielectric material, 1330-1, 1330-2, . . . , 1330-N, a semiconductormaterial, 1332-1, 1332-2, . . . , 1332-N, and a second dielectricmaterial, 1333-1, 1333-2, . . . , 1333-N, along and in which thehorizontally oriented access devices and horizontally oriented storagenodes, e.g., capacitor cells, can be formed within the layers ofsemiconductor material, 1332-1, 1332-2, . . . , 1332-N. In the exampleembodiment of FIG. 13A, the horizontally oriented storage nodes, e.g.,capacitor cells, are illustrated as having been formed in thissemiconductor fabrication process and first electrodes 1361, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1356, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1363, are shown. However, embodiments are not limitedto this example. In other embodiments, the first electrodes 1361, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1356, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1363, may be formed subsequent to forming a firstsource/drain region, a channel region, and a second source/drain regionin a region of the semiconductor material, 1332-1, 1332-2, . . . ,1332-N, intended for location, e.g., placement formation, of thehorizontally oriented access devices, described next.

In the example embodiment of FIG. 13A, the horizontally oriented storagenodes having the first electrodes 1361, e.g., bottom electrodes to becoupled to source/drain regions of horizontal access devices, and secondelectrodes 1356, e.g., top electrodes to be coupled to a commonelectrode plane such as a ground plane, are shown formed in a secondhorizontal opening, e.g., 1179 shown in FIG. 11C, extending in seconddirection (D2), left and right in the plane of the drawing sheet, athird distance from the vertical opening, e.g., 1151 in FIG. 11C, formedin the vertical stack, e.g., 401 in FIG. 4, and along an axis oforientation of the horizontal access devices and horizontal storagenodes of the arrays of vertically stacked memory cells of the threedimensional (3D) memory. In FIG. 13A, a neighboring, horizontal accessline 1377 is illustrated adjacent the second dielectric material,1333-1, 1333-2, . . . , 1333-N, and the fourth dielectric material1374-1, 1374-2, . . . , 1374-N, and below the semiconductor material,1332-1, 1332-2, . . . , 1332-N, indicating a location set inward fromthe plane and orientation of the drawing sheet.

In some embodiments, the fourth dielectric material 1374 may be belowthe first dielectric material 1330 while remaining in direct contactwith the first conductive material 1377, and the low doped semiconductormaterial 1332. An opening where second conductive material 1341 may bevertically deposited is shown.

FIG. 13B illustrates an alternate cross sectional view, taken alongcut-line B-B′ in FIG. 12A, showing another view of the semiconductorstructure at this particular point in one example semiconductorfabrication process of an embodiment of the present disclosure. Thecross sectional view shown in FIG. 13B is illustrated extending in thesecond horizontal direction (D2) 1305, left and right along the plane ofthe drawing sheet, along an axis of the repeating iterations ofalternating layers of a first dielectric material, 1330-1, 1330-2, . . ., 1330-N, a semiconductor material, 1332-1, 1332-2, . . . , 1332-N, anda second dielectric material, 1333-1, 1333-2, . . . , 1333-N, along andin which the horizontally oriented access devices and horizontallyoriented storage nodes, e.g., capacitor cells, can be formed within thelayers of semiconductor material, 1332-1, 1332-2, . . . , 1332-N. In theexample embodiment of FIG. 13B, the horizontally oriented storage nodes,e.g., capacitor cells, are illustrated as having been formed in thissemiconductor fabrication process and first electrodes 1361, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1356, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1363, are shown. However, embodiments are not limitedto this example. In other embodiments, the first electrodes 1361, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1356, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1363, may be formed subsequent to forming a firstsource/drain region, a channel region, and a second source/drain regionin a region of the semiconductor material, 1332-1, 1332-2, . . . ,1332-N, intended for location, e.g., placement formation, of thehorizontally oriented access devices, described next.

In the example embodiment of FIG. 13B, the horizontally oriented storagenodes having the first electrodes 1361, e.g., bottom electrodes to becoupled to source/drain regions of horizontal access devices, and secondelectrodes 1356, e.g., top electrodes to be coupled to a commonelectrode plane such as a ground plane, are shown formed in a secondhorizontal opening, extending in second direction (D2), left and rightin the plane of the drawing sheet, a third distance from the verticalopening, e.g., 1251 in FIG. 12B, formed in the vertical stack, e.g., 401in FIG. 4, and along an axis of orientation of the horizontal accessdevices and horizontal storage nodes of the arrays of vertically stackedmemory cells of the three dimensional (3D) memory. In FIG. 13B, aneighboring, horizontal access line 1377 is illustrated adjacent thesecond dielectric material, 1333-1, 1333-2, . . . , 1333-N, and thefourth dielectric material 1374-1, 1374-2, . . . , 1374-N, and below thesemiconductor material, 1332-1, 1332-2, . . . , 1332-N, indicating alocation set inward from the plane and orientation of the drawing sheet.

The first conductive material 1377 may remain in direct electricalcontact on a top surface of the semiconductor material, 1332-1, 1332-2,. . . , 1332-N. In some embodiments, the fourth dielectric material 1374may be formed below the first dielectric material 1330 while remainingin direct contact with the first conductive material 1377, the firstsource/drain region 1375, and the low doped semiconductor material 1332.

The second conductive material 1341 may be formed as a vertical digitline adjacent first conductive material 1377-1, 1377-2, . . . , 1377-Nand high doped semiconductor material 1395 in second vertical opening1370. The second conductive material 1341 may intersect first dielectricmaterial, 1330-1, 1330-2, . . . , 1330-N, the fourth dielectric material1374-1, 1374-2, . . . , 1374-N, and low doped semiconductor material1332-1, 1332-2, . . . , 1332-N. The second conductive material 1341 mayform vertically oriented digit lines adjacent a first source/drainregion 1375.

In some embodiments, the second conductive material 1341 may be formedfrom a silicide. In some embodiments, the second conductive material1341 may comprise a titanium material. In some embodiments, the secondconductive material 1341 may comprise a titanium nitride (TiN) material.In some embodiments, the second conductive material 1341 may comprise aRuthenium (Ru) material. In some embodiments, the second conductivematerial 1341 may be tungsten (W).

In one embodiment, the second conductive material 1341 may be formed bygas phase doping a high energy gas phase dopant, such as phosphorus (P)atoms, as impurity dopants, at a high plasma energy such as PECVD toform a high concentration, n-type doped (n+) region within the thirdvertical opening 1381. A polysilicon material may be deposited into thethird vertical opening 1381. For example, a highly phosphorus (P) doped(n+) poly-silicon germanium (SiGe) material into the third verticalopenings 1381 to form the second conductive material 1341.

The first source/drain region 1375 may be formed by out-diffusing n-type(n+) dopants into the semiconductor material, 1332-1, 1332-2, . . . ,1332-N. In one embodiment, the plurality of patterned third verticalopenings may be adjacent the first source/drain region 1375 and the highconcentration, n-type dopant may be out-diffused into the low dopedsemiconductor material, 1332-1, 1332-2, . . . , 1332-N, to form thefirst source/drain region 1375. The first source/drain region 1375 maybe formed on the low doped semiconductor material 1332, on both sides ofvertical second conductive material 1341. Fourth dielectric material1374 may be below the first dielectric material 1330 while remaining indirect contact with the first conductive material 1377, the firstsource/drain region, and the low doped semiconductor material 1332.

FIG. 14A illustrates a cross sectional view, taken along cut-line B-B′in FIG. 12A, showing another view of the semiconductor structure at thisparticular point in one example semiconductor fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 14A is illustrated extending in the second horizontal direction(D2) 1405, left and right along the plane of the drawing sheet, along anaxis of the repeating iterations of alternating layers of a firstdielectric material, 1430-1, 1430-2, . . . , 1430-N, a semiconductormaterial, 1432-1, 1432-2, . . . , 1432-N, and a second dielectricmaterial, 1433-1, 1433-2, . . . , 1433-N, along and in which thehorizontally oriented access devices and horizontally oriented storagenodes, e.g., capacitor cells, can be formed within the layers ofsemiconductor material, 1432-1, 1432-2, . . . , 1432-N. In the exampleembodiment of FIG. 14A, the horizontally oriented storage nodes, e.g.,capacitor cells, are illustrated as having been formed in thissemiconductor fabrication process and first electrodes 1461, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1456, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1463, are shown. However, embodiments are not limitedto this example. In other embodiments, the first electrodes 1461, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1456, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1463, may be formed subsequent to forming a firstsource/drain region 1475, a channel region, and a second source/drainregion in a region of the semiconductor material, 1432-1, 1432-2, . . ., 1432-N, intended for location, e.g., placement formation, of thehorizontally oriented access devices, described next.

In the example embodiment of FIG. 14A, the horizontally oriented storagenodes having the first electrodes 1461, e.g., bottom electrodes to becoupled to source/drain regions of horizontal access devices, and secondelectrodes 1456, e.g., top electrodes to be coupled to a commonelectrode plane such as a ground plane, are shown formed in a secondhorizontal opening, e.g., 1179 shown in FIG. 11C, extending in seconddirection (D2), left and right in the plane of the drawing sheet, athird distance from the vertical opening, e.g., 1151 in FIG. 11C, formedin the vertical stack, e.g., 401 in FIG. 4, and along an axis oforientation of the horizontal access devices and horizontal storagenodes of the arrays of vertically stacked memory cells of the threedimensional (3D) memory. In FIG. 14A, a neighboring, horizontal accessline 1477 is illustrated adjacent the second dielectric material,1433-1, 1433-2, . . . , 1433-N, and the fourth dielectric material1474-1, 1474-2, . . . , 1474-N, and below the semiconductor material,1432-1, 1432-2, . . . , 1432-N, indicating a location set inward fromthe plane and orientation of the drawing sheet.

In some embodiments, the fourth dielectric material 1474 may be belowthe first dielectric material 1430 while remaining in direct contactwith the first conductive material 1477 and the low doped semiconductormaterial 1432. The first source/drain region 1475 may be formed on thelow doped semiconductor material 1432, on both sides of vertical secondconductive material 1441.

A metal material 1471 may be deposited into the third vertical opening1481. In some embodiments, the metal material 1471 may comprise one ormore of a doped semiconductor, e.g., doped silicon, doped germanium,etc., a conductive metal nitride, e.g., titanium nitride, tantalumnitride, etc., a metal, e.g., tungsten (W), titanium (Ti), tantalum(Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc., and/or ametal-semiconductor compound, e.g., tungsten silicide, cobalt silicide,titanium silicide, etc, and/or some other combination thereof.

The second conductive material 1441 may be formed vertically through athird vertical openings 1481, on the outside of the metal material 1471.The second conductive material 1441 may be formed from a highconcentration, n-type dopant. The high concentration, n-type dopant maybe formed by depositing a polysilicon material onto the secondconductive material 1441. For example, the high concentration, n-typedopant may be formed by depositing a highly phosphorus (P) doped (n+)poly-silicon germanium (SiGe) material onto the second conductivematerial 1441. The second conductive material 1441 coupled to the metalmaterial 1471 may be formed vertically adjacent first conductivematerial 1477-1, 1477-2, . . . , 1477-N and high doped semiconductormaterial 1495 in second vertical opening 1470. The second conductivematerial 1441 coupled with the metal material 1471 may intersect firstdielectric material, 1430-1, 1430-2, . . . , 1430-N, first source/drainregion 1475, the fourth dielectric material 1474-1, 1474-2, . . . ,1474-N, and low doped semiconductor material 1432-1, 1432-2, . . . ,1432-N.

FIG. 14B illustrates an alternate cross sectional view, taken alongcut-line B-B′ in FIG. 12A, showing another view of the semiconductorstructure at this particular point in one example semiconductorfabrication process of an embodiment of the present disclosure. Thecross sectional view shown in FIG. 14B is illustrated extending in thesecond horizontal direction (D2) 1405, left and right along the plane ofthe drawing sheet, along an axis of the repeating iterations ofalternating layers of a first dielectric material, 1430-1, 1430-2, . . ., 1430-N, a semiconductor material, 1432-1, 1432-2, . . . , 1432-N, anda second dielectric material, 1433-1, 1433-2, . . . , 1433-N, along andin which the horizontally oriented access devices and horizontallyoriented storage nodes, e.g., capacitor cells, can be formed within thelayers of semiconductor material, 1432-1, 1432-2, . . . , 1432-N. In theexample embodiment of FIG. 14B, the horizontally oriented storage nodes,e.g., capacitor cells, are illustrated as having been formed in thissemiconductor fabrication process and first electrodes 1461, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1456, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1463, are shown. However, embodiments are not limitedto this example. In other embodiments the first electrodes 1461, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1456, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1463, may be formed subsequent to forming a secondconductive material coupled to a source/drain region and a channelregion, in a region of the semiconductor material, 1432-1, 1432-2, . . ., 1432-N, intended for location, e.g., placement formation, of thehorizontally oriented access devices, described next.

In the example embodiment of FIG. 14B, the horizontally oriented storagenodes having the first electrodes 1461, e.g., bottom electrodes to becoupled to source/drain regions of horizontal access devices, and secondelectrodes 1456, e.g., top electrodes to be coupled to a commonelectrode plane such as a ground plane, are shown formed in a secondhorizontal opening, e.g., 1179 shown in FIG. 11C, extending in seconddirection (D2), left and right in the plane of the drawing sheet, athird distance from the vertical opening, e.g., 1151 in FIG. 11C, formedin the vertical stack, e.g., 401 in FIG. 4, and along an axis oforientation of the horizontal access devices and horizontal storagenodes of the arrays of vertically stacked memory cells of the threedimensional (3D) memory. In FIG. 14B, a neighboring, horizontal accessline 1477-3 is illustrated adjacent the second dielectric material,1433-1, 1433-2, . . . , 1433-N, and the fourth dielectric material1474-1, 1474-2, . . . , 1474-N, and below the semiconductor material,1432-1, 1432-2, . . . , 1432-N, indicating a location set inward fromthe plane and orientation of the drawing sheet.

In some embodiments, the fourth dielectric material 1474 may be belowthe first dielectric material 1430 while remaining in direct contactwith the first conductive material 1477 and the low doped semiconductormaterial 1432. The first source/drain region 1475 may be formed on thelow doped semiconductor material 1432, on both sides of vertical secondconductive material 1441.

A metal material 1471 may be deposited into the third vertical opening1481. In some embodiments, the metal material 1471 may comprise one ormore of a doped semiconductor, e.g., doped silicon, doped germanium,etc., a conductive metal nitride, e.g., titanium nitride, tantalumnitride, etc., a metal, e.g., tungsten (W), titanium (Ti), tantalum(Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc., and/or ametal-semiconductor compound, e.g., tungsten silicide, cobalt silicide,titanium silicide, etc, and/or some other combination thereof.

The second conductive material 1441 may be coupled indistinguishablywith the metal material 1471 within third vertical openings 1481. Thesecond conductive material 1441 may be formed from a high concentration,n-type dopant. The high concentration, n-type dopant may be formed bydepositing a polysilicon material onto the second conductive material1441. For example, the high concentration, n-type dopant may be formedby depositing a highly phosphorus (P) doped (n+) poly-silicon germanium(SiGe) material onto the second conductive material 1441. The secondconductive material 1441 coupled to the metal material 1471 may beformed vertically adjacent first conductive material 1477-1, 1477-2, . .. , 1477-N and high doped semiconductor material 1495 in second verticalopening 1470. The second conductive material 1441 coupled with the metalmaterial 1471 may intersect first dielectric material, 1430-1, 1430-2, .. . , 1430-N, first source/drain region 1475, the fourth dielectricmaterial 1474-1, 1474-2, . . . , 1474-N, and low doped semiconductormaterial 1432-1, 1432-2, . . . , 1432-N.

FIG. 15 illustrates an alternate cross sectional view, taken alongcut-line B-B′ in FIG. 12A, showing a view of the semiconductor structureat this particular point in one example semiconductor fabricationprocess of an embodiment of the present disclosure. The cross sectionalview shown in FIG. 15 is illustrated extending in the second horizontaldirection (D2) 1505, left and right along the plane of the drawingsheet, along an axis of the repeating iterations of alternating layersof a first dielectric material, 1530-1, 1530-2, . . . , 1530-N, asemiconductor material, 1532-1, 1532-2, . . . , 1532-N, and a seconddielectric material, 1533-1, 1533-2, . . . , 1533-N, along and in whichthe horizontally oriented access devices and horizontally orientedstorage nodes, e.g., capacitor cells, can be formed within the layers ofsemiconductor material, 1532-1, 1532-2, . . . , 1532-N. In the exampleembodiment of FIG. 15, the horizontally oriented storage nodes, e.g.,capacitor cells, are illustrated as having been formed in thissemiconductor fabrication process and first electrodes 1561, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1556, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1563, are shown. However, embodiments are not limitedto this example. In other embodiments, the first electrodes 1561, e.g.,bottom electrodes to be coupled to source/drain regions of horizontalaccess devices, and second electrodes 1556, e.g., top electrodes to becoupled to a common electrode plane such as a ground plane, separated bycell dielectrics 1563, may be formed subsequent to forming a firstsource/drain region, a channel region, and a second source/drain regionin a region of the semiconductor material, 1532-1, 1532-2, . . . ,1532-N, intended for location, e.g., placement formation, of thehorizontally oriented access devices, described next.

In the example embodiment of FIG. 15, the horizontally oriented storagenodes having the first electrodes 1561, e.g., bottom electrodes to becoupled to source/drain regions of horizontal access devices, and secondelectrodes 1556, e.g., top electrodes to be coupled to a commonelectrode plane such as a ground plane, are shown formed in a secondhorizontal opening, extending in second direction (D2), left and rightin the plane of the drawing sheet, a third distance from the verticalopening, e.g., 1251 in FIG. 12B, formed in the vertical stack, e.g., 401in FIG. 4, and along an axis of orientation of the horizontal accessdevices and horizontal storage nodes of the arrays of vertically stackedmemory cells of the three dimensional (3D) memory. In FIG. 15, aneighboring, horizontal access line 1577 is illustrated adjacent thesecond dielectric material, 1533-1, 1533-2, . . . , 1533-N, and thefourth dielectric material 1574-1, 1574-2, . . . , 1574-N, and below thesemiconductor material, 1532-1, 1532-2, . . . , 1532-N, indicating alocation set inward from the plane and orientation of the drawing sheet.

In some embodiments, the fourth dielectric material 1574 may be belowthe first dielectric material 1530 while remaining in direct contactwith the first conductive material 1577, and the low doped semiconductormaterial 1532.

The second conductive material 1541 may be formed vertically through athird vertical openings 1581. The second conductive material 1541 may beformed as a vertical digit line adjacent first conductive material1577-1, 1577-2, . . . , 1577-N and high doped semiconductor material1595 in second vertical opening 1570. The second conductive material1541 may intersect first dielectric material, 1530-1, 1530-2, . . . ,1530-N, the fourth dielectric material 1574-1, 1574-2, . . . , 1574-N,and low doped semiconductor material 1532-1, 1532-2, . . . , 1532-N. Thethird vertical openings 1581 may be formed past (e.g., through) thesubstrate 1500 to underlying interconnection metal layers such that thesecond conductive material 1541 may be connected to underlying CMOS andinterconnection layers beneath the substrate 1500. The connection to theunderlying metal layers may provide a shorter path for the secondconductive material 1541 to CMOS circuitry beneath the substrate 1500.

FIG. 16A illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines, such as illustrated in FIGS. 1-3,and in accordance with a number of embodiments of the presentdisclosure. FIG. 16A illustrates a top down view of a semiconductorstructure, at a particular point in time, in a semiconductor fabricationprocess, according to one or more embodiments. In the example embodimentof FIG. 16A, the method comprises using a photolithographic process topattern the photolithographic mask 1637 where a second conductivematerial 1641 is asymmetric to reserve room for a body contact 1695. Themethod in FIG. 16A further illustrates using one or more etchantprocesses to form a vertical opening 1651 in a storage node region 1650through the vertical stack and extending predominantly in the firsthorizontal direction (D1) 1609. The one or more etchant processes formsa vertical opening 1651 to expose third sidewalls in the repeatingiterations of alternating layers of a first dielectric material, 1630-1,1630-2, . . . , 1630-N, a semiconductor material, 1632-1, 1632-2, . . ., 1632-N, and a second dielectric material, 1633-1, 1633-2, . . . ,1633-N, in the vertical stack, adjacent a second region of thesemiconductor material.

According to an example embodiment, the method comprises selectivelyetching the second region of the semiconductor material, 1632-1, 1632-2,. . . , 1632-N, to deposit a second source/drain region and capacitorcells through the second horizontal opening, which is a secondhorizontal distance back from a vertical opening 1651 in the verticalstack. In some embodiments, the method comprises forming capacitor cellas the storage node in the second horizontal opening. By way of example,and not by way of limitation, forming the capacitor comprises using anatomic layer deposition (ALD) process to sequentially deposit, in thesecond horizontal opening, a first electrode 1661 and a second electrode1656 separated by a cell dielectric 1663. Other suitable semiconductorfabrication techniques and/or storage nodes structures may be used.

In other embodiments, the method further comprises forming a firstsource/drain region and second conductive material 1641 through thirdvertical openings 1681. A second conductive material 1641 may be formedvertically through a plurality of patterned third vertical openings 1681through the vertical stack. The vertically oriented digit lines areformed asymmetrically adjacent in electrical contact with the firstsource/drain regions 1675. The second conductive material 1641 may beformed as an asymmetric vertical digit line contact to reserve room fora body contact 1695. The high doped semiconductor material 1695 may beformed within a second vertical opening 1670 as the body contact. Thehigh doped semiconductor material 1695 may form a body contact for thesecond conductive material 1641, the hard mask 1637, and the fourthdielectric material 1674. The second conductive material 1641 may formvertical digit lines adjacent a first source/drain region 1675. Thefirst source/drain region 1675 may be formed adjacent a first conductivematerial 1677 and surrounding the plurality of patterned third verticalopenings 1681. The first conductive material 1677 may form a lateralaccess line between the first vertical openings and the etched fourthdielectric material 1674.

FIG. 16B illustrates an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells, having horizontally oriented access devices andhorizontally oriented access lines, such as illustrated in FIGS. 1-3,and in accordance with a number of embodiments of the presentdisclosure. FIG. 16B illustrates a top down view of a semiconductorstructure, at a particular point in time, in a semiconductor fabricationprocess, according to one or more embodiments. In the example embodimentof FIG. 16B, the method comprises using a photolithographic process topattern the photolithographic mask 1637 where a second conductivematerial 1641 is deposited symmetrically. The method in FIG. 16B furtherillustrates using one or more etchant processes to form a verticalopening 1651 in a storage node region 1650 through the vertical stackand extending predominantly in the first horizontal direction (D1) 1609.The one or more etchant processes forms a vertical opening 1651 toexpose third sidewalls in the repeating iterations of alternating layersof a first dielectric material, 1630-1, 1630-2, . . . , 1630-N, asemiconductor material, 1632-1, 1632-2, . . . , 1632-N, and a seconddielectric material, 1633-1, 1633-2, . . . , 1633-N, in the verticalstack, adjacent a second region of the semiconductor material.

According to an example embodiment, the method comprises selectivelyetching the second region of the semiconductor material, 1632-1, 1632-2,. . . , 1632-N, to deposit a second source/drain region and capacitorcells through the second horizontal opening, which is a secondhorizontal distance back from a vertical opening 1651 in the verticalstack. In some embodiments, the method comprises forming capacitor cellas the storage node in the second horizontal opening. By way of example,and not by way of limitation, forming the capacitor comprises using anatomic layer deposition (ALD) process to sequentially deposit, in thesecond horizontal opening, a first electrode 1661 and a second electrode1656 separated by a cell dielectric 1663. Other suitable semiconductorfabrication techniques and/or storage nodes structures may be used.

In other embodiments, the method further comprises forming a firstsource/drain region and second conductive material 1641 through thirdvertical openings 1681. A second conductive material 1641 may be formedvertically through a plurality of patterned third vertical openings 1681through the vertical stack. The second conductive material 1641 may beformed symmetrically as a vertical digit line contact. The verticallyoriented digit lines are formed symmetrically, in vertical alignment, inelectrical contact with the first source/drain regions 1675. The secondconductive material 1641 may be formed in contact with an insulatormaterial 1692 such that there is no body contact within a secondvertical opening 1670. Second conductive material 1641 may form verticaldigit lines adjacent a first source/drain region 1675. The firstsource/drain region 1675 may be formed adjacent a first conductivematerial 1677 and surrounding the plurality of patterned third verticalopenings 1681. The first conductive material 1677 may form a lateralaccess line between the first vertical openings and the etched fourthdielectric material 1674.

FIG. 17A illustrates an alternate top view, showing another view of thesemiconductor structure at this particular point in one examplesemiconductor fabrication process, and in accordance with a number ofembodiments of the present disclosure. FIG. 17A illustrates a top downview of a semiconductor structure with dual vertical digit lines. Asillustrated in FIG. 17A, embodiments of the present disclosure may beemployed in a structure wherein the array of vertically stacked memorycells is electrically coupled in a folded digit line architecture. In afolded digit line structure, the dual structures may share a single wordline 1703. A folded digit line structure may be possible when the digitlines 1707 has an odd amount of word lines 1703. A folded digit linestructure may be possible when only one word line is turned on in thesub array block.

FIG. 17B illustrates an alternate top view, showing another view of thesemiconductor structure at this particular point in one examplesemiconductor fabrication process, and in accordance with a number ofembodiments of the present disclosure. FIG. 17B illustrates a top downview of a semiconductor structure with dual vertical digit lines. Asillustrated in FIG. 17B, embodiments of the present disclosure may beemployed in a structure wherein the array of vertically stacked memorycells is electrically coupled in an open digit line architecture. In anopen digit line structure, each digit line structure may have its ownword line 1703, such that a dual vertical digit line structure may havetwo wordlines. An open digit line structure may be possible when thedigit lines 1707 has an even amount of word lines 1703. If twoneighboring wordlines are turned on, only an open digit line structuremay be possible; a folded digit line structure would not be possible.

FIG. 18 is a block diagram of an apparatus in the form of a computingsystem 1800 including a memory device 1803 in accordance with a numberof embodiments of the present disclosure. As used herein, a memorydevice 1803, a memory array 1810, and/or a host 1802, for example, mightalso be separately considered an “apparatus.” According to embodiments,the memory device 1802 may comprise at least one memory array 1810 witha memory cell formed having a digit line and body contact, according tothe embodiments described herein.

In this example, system 1800 includes a host 1802 coupled to memorydevice 1803 via an interface 1804. The computing system 1800 can be apersonal laptop computer, a desktop computer, a digital camera, a mobiletelephone, a memory card reader, or an Internet-of-Things (IoT) enableddevice, among various other types of systems. Host 1802 can include anumber of processing resources (e.g., one or more processors,microprocessors, or some other type of controlling circuitry) capable ofaccessing memory 1803. The system 1800 can include separate integratedcircuits, or both the host 1802 and the memory device 1803 can be on thesame integrated circuit. For example, the host 1802 may be a systemcontroller of a memory system comprising multiple memory devices 1803,with the system controller 1805 providing access to the respectivememory devices 1803 by another processing resource such as a centralprocessing unit (CPU).

In the example shown in FIG. 18, the host 1802 is responsible forexecuting an operating system (OS) and/or various applications (e.g.,processes) that can be loaded thereto (e.g., from memory device 1803 viacontroller 1805). The OS and/or various applications can be loaded fromthe memory device 1803 by providing access commands from the host 1802to the memory device 1803 to access the data comprising the OS and/orthe various applications. The host 1802 can also access data utilized bythe OS and/or various applications by providing access commands to thememory device 1803 to retrieve said data utilized in the execution ofthe OS and/or the various applications.

For clarity, the system 1800 has been simplified to focus on featureswith particular relevance to the present disclosure. The memory array1810 can be a DRAM array comprising at least one memory cell having adigit line and body contact formed according to the techniques describedherein. For example, the memory array 1810 can be an unshielded DL 4F2array such as a 3D-DRAM memory array. The array 1810 can comprise memorycells arranged in rows coupled by word lines (which may be referred toherein as access lines or select lines) and columns coupled by digitlines (which may be referred to herein as sense lines or data lines).Although a single array 1810 is shown in FIG. 18, embodiments are not solimited. For instance, memory device 1803 may include a number of arrays1810 (e.g., a number of banks of DRAM cells).

The memory device 1803 includes address circuitry 1806 to latch addresssignals provided over an interface 1804. The interface can include, forexample, a physical interface employing a suitable protocol (e.g., adata bus, an address bus, and a command bus, or a combineddata/address/command bus). Such protocol may be custom or proprietary,or the interface 1804 may employ a standardized protocol, such asPeripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, or thelike. Address signals are received and decoded by a row decoder 1808 anda column decoder 1812 to access the memory array 1810. Data can be readfrom memory array 1810 by sensing voltage and/or current changes on thesense lines using sensing circuitry 1811. The sensing circuitry 1811 cancomprise, for example, sense amplifiers that can read and latch a page(e.g., row) of data from the memory array 1810. The I/O circuitry 1807can be used for bi-directional data communication with the host 1802over the interface 1804. The read/write circuitry 1813 is used to writedata to the memory array 1810 or read data from the memory array 1810.As an example, the circuitry 1813 can comprise various drivers, latchcircuitry, etc.

Control circuitry 1805 decodes signals provided by the host 1802. Thesignals can be commands provided by the host 1802. These signals caninclude chip enable signals, write enable signals, and address latchsignals that are used to control operations performed on the memoryarray 1810, including data read operations, data write operations, anddata erase operations. In various embodiments, the control circuitry1805 is responsible for executing instructions from the host 1802. Thecontrol circuitry 1805 can comprise a state machine, a sequencer, and/orsome other type of control circuitry, which may be implemented in theform of hardware, firmware, or software, or any combination of thethree. In some examples, the host 1802 can be a controller external tothe memory device 1803. For example, the host 1802 can be a memorycontroller which is coupled to a processing resource of a computingdevice.

The term semiconductor can refer to, for example, a material, a wafer,or a substrate, and includes any base semiconductor structure.“Semiconductor” is to be understood as including silicon-on-sapphire(SOS) technology, silicon-on-insulator (SOI) technology,thin-film-transistor (TFT) technology, doped and undoped semiconductors,epitaxial silicon supported by a base semiconductor structure, as wellas other semiconductor structures. Furthermore, when reference is madeto a semiconductor in the preceding description, previous process stepsmay have been utilized to form regions/junctions in the basesemiconductor structure, and the term semiconductor can include theunderlying materials containing such regions/junctions.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the drawing figure number and theremaining digits identify an element or component in the drawing.Similar (e.g., the same) elements or components between differentfigures may be identified by the use of similar digits. As will beappreciated, elements shown in the various embodiments herein can beadded, exchanged, and/or eliminated so as to provide a number ofadditional embodiments of the present disclosure. In addition, as willbe appreciated, the proportion and the relative scale of the elementsprovided in the figures are intended to illustrate the embodiments ofthe present disclosure and should not be taken in a limiting sense.

As used herein, “a number of” or a “quantity of” something can refer toone or more of such things. For example, a number of or a quantity ofmemory cells can refer to one or more memory cells. A “plurality” ofsomething intends two or more. As used herein, multiple acts beingperformed concurrently refers to acts overlapping, at least in part,over a particular time period. As used herein, the term “coupled” mayinclude electrically coupled, directly coupled, and/or directlyconnected with no intervening elements (e.g., by direct physicalcontact), indirectly coupled and/or connected with intervening elements,or wirelessly coupled. The term coupled may further include two or moreelements that co-operate or interact with each other (e.g., as in acause and effect relationship). An element coupled between two elementscan be between the two elements and coupled to each of the two elements.

It should be recognized the term vertical accounts for variations from“exactly” vertical due to routine manufacturing, measuring, and/orassembly variations and that one of ordinary skill in the art would knowwhat is meant by the term “perpendicular.” For example, the vertical cancorrespond to the z-direction. As used herein, when a particular elementis “adjacent to” an other element, the particular element can cover theother element, can be over the other element or lateral to the otherelement and/or can be in direct physical contact the other element.Lateral to may refer to the horizontal direction (e.g., the y-directionor the x-direction) that may be perpendicular to the z-direction, forexample.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of various embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of skill in the art uponreviewing the above description. The scope of the various embodiments ofthe present disclosure includes other applications in which the abovestructures and methods are used. Therefore, the scope of variousembodiments of the present disclosure should be determined withreference to the appended claims, along with the full range ofequivalents to which such claims are entitled.

1. A method for forming arrays of vertically stacked memory cells,having horizontally oriented access devices and access lines andvertically oriented digit lines, comprising: forming a plurality offirst vertical openings, having a first horizontal direction and asecond horizontal direction, through a vertical stack of repeatingiterations of a first dielectric material, a semiconductor material, anda second dielectric material, the first vertical openings extendingpredominantly in the second horizontal direction to form elongatedvertical, pillar columns with first vertical sidewalls in the stack;filling the plurality of first vertical openings with a third dielectricmaterial; forming a second vertical opening through the vertical stackand extending predominantly in the first horizontal direction to exposesecond vertical sidewalls adjacent a first region of the semiconductormaterial; selectively etching the second dielectric material in thesecond horizontal direction to form a plurality of first horizontalopenings; removing a portion of the third dielectric material filled inthe plurality of first vertical openings, between the first horizontalopenings, to form continuous second horizontal openings extending in thefirst horizontal direction; depositing a first conductive material on agate dielectric material, recessed back, in the continuous secondhorizontal openings to form horizontally oriented access lines opposinga channel region of the semiconductor material; and forming a pluralityof patterned third vertical openings through the vertical stack adjacentfirst source/drain regions in which to deposit a second conductivematerial to form vertically oriented digit lines.
 2. The method of claim1, further comprising depositing a tungsten (W) material as the secondconductive material to form vertically oriented digit lines.
 3. Themethod of claim 1, further comprising: gas phase doping a dopant in atop surface of the semiconductor material to form the first source/drainregion horizontally adjacent the channel region; and depositing a fourthdielectric material in the continuous second horizontal openingsadjacent the conductive material and the gate dielectric material. 4.The method of claim 1, further comprising: forming a fourth verticalopening adjacent a second region of the semiconductor material to exposethird vertical sidewalls in the vertical stack; selectively etching thesemiconductor material in the second horizontal direction to form aplurality of third horizontal openings in the second region; gas phasedoping a dopant in a side surface of the semiconductor material from thethird horizontal openings to form second source/drain regionshorizontally adjacent the channel region; and depositing horizontallyoriented capacitor cells having a bottom electrode formed in electricalcontact with the second source/drain regions.
 5. The method of claim 1,wherein selectively etching the second dielectric material comprisesremoving the second dielectric material a first distance (DIST 1) in arange of approximately fifty (50) to one hundred and fifty (150)nanometers (nm) back from the second vertical opening.
 6. The method ofclaim 1, further comprising selectively recessing the conductivematerial and the gate dielectric material in the second direction asecond distance (DIST 2) in a range of twenty (20) to fifty (50)nanometers (nm) back from the second vertical opening.
 7. The method ofclaim 1, further comprising selectively recessing the conductivematerial and the gate dielectric material a second distance (DIST 2)back into the continuous second horizontal openings extending in thefirst horizontal direction using an atomic layer etching (ALE) process.8. The method of claim 1, wherein depositing a conductive material on agate dielectric material, recessed back, in the continuous secondhorizontal openings extending in the first horizontal directioncomprises depositing the gate dielectric and the conductive materialusing an atomic layer deposition (ALD) process.
 9. The method of claim1, further comprising depositing a high doped semiconductor materialinto the second vertical opening to form a conductive body contact tothe semiconductor material.
 10. The method of claim 1, furthercomprising depositing layers of an oxide material as the firstdielectric material, a low doped, p-type (p−) polysilicon as thesemiconductor material, and a silicon nitride (SiN) material as thesecond dielectric material, in repeating iterations vertically, to formthe vertical stack.
 11. The method of claim 1, further comprisingdepositing a ruthenium (Ru) composition as the second conductivematerial to form vertically oriented digit lines.
 12. A method forforming arrays of vertically stacked memory cells, having horizontallyoriented access devices and access lines and vertically oriented digitlines, comprising: forming a plurality of first vertical openings,having a first horizontal direction and a second horizontal direction,through a vertical stack of repeating iterations of a first dielectricmaterial, a semiconductor material, and a second dielectric material,the first vertical openings extending predominantly in the secondhorizontal direction to form elongated vertical, pillar columns withfirst vertical sidewalls in the stack; filling the plurality of firstvertical openings with a third dielectric material; forming a secondvertical opening through the vertical stack and extending predominantlyin the first horizontal direction to expose second vertical sidewallsadjacent a first region of the semiconductor material; selectivelyetching the second dielectric material in the second horizontaldirection to form a plurality of first horizontal openings, separatedvertically and horizontally in the stack, and separated horizontally bythe third dielectric material; removing a portion of the thirddielectric material filled in the plurality of first vertical openings,laterally in-between the first horizontal openings extending in thesecond horizontal direction, to form continuous second horizontalopenings extending in the first horizontal direction; depositing aconductive material on a gate dielectric material, recessed back, in thecontinuous second horizontal openings to form horizontally orientedaccess lines opposing a channel region of the semiconductor material;patterning third vertical openings through the vertical stack proximatefirst source/drain regions; and depositing a polysilicon material havinga high concentration of an n-type (n+) dopant in the patterned thirdvertical openings.
 13. The method of claim 12, wherein forming theplurality of patterned third vertical openings through the verticalstack comprises forming the plurality of patterned third verticalopenings in vertical alignment with a location of the first source/drainregions to serve as the first source/drain regions.
 14. The method ofclaim 12, wherein forming the plurality of patterned third verticalopenings through the vertical stack comprises forming the plurality ofpatterned third vertical openings adjacent a location of the firstsource/drain regions and out-diffusing the n-type (n+) dopant into thesemiconductor material to form the first source/drain regions.
 15. Themethod of claim 12, further comprising depositing a tungsten (W)material on the polysilicon material in the patterned third verticalopenings.
 16. The method of claim 12, further comprising depositing atitanium/titanium nitride (TiN) conductive material on the polysiliconmaterial, via the patterned third vertical openings, to form a titaniumsilicide as part of the vertically oriented digit line coupled to firstsource/drain regions of the horizontally oriented access devices. 17.The method of claim 12, wherein depositing a polysilicon material havinga high concentration of an n-type (n+) dopant in the patterned thirdvertical openings comprises depositing a highly phosphorus (P) doped(n+) poly-silicon germanium (SiGe) material.
 18. A memory device,comprising: an array of vertically stacked memory cells, the arrayhaving horizontally oriented access devices and access lines andvertically oriented digit lines, comprising: horizontally orientedaccess devices having a first source/drain region and a second sourcedrain region separated by a channel region, and gates opposing thechannel region and separated therefrom by a gate dielectric;horizontally oriented access lines coupled to the gates and separatedfrom the channel region by the gate dielectric; horizontally orientedstorage nodes electrically coupled to the second source/drain regions ofthe horizontally oriented access devices; and vertically oriented digitlines electrically coupled to the first source/drain regions of thehorizontally oriented access devices.
 19. The memory device of claim 18,wherein the vertically oriented digit lines comprise a highly phosphorus(P) doped (n+) poly-silicon germanium (SiGe) material.
 20. The memorydevice of claim 18, wherein the vertically oriented digit lines comprisea tungsten (W) material formed on a titanium/titanium nitride (TiN)material which forms a titanium silicide with the first source/drainregions of the horizontally oriented access devices.